coreboot

Author	SHA1	Message	Date
Edward O'Callaghan	e408dced63	Redundant addr '&' operator on func ptr's in struct initiator Bring code inline to be consistent with the rest of coreboot. See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase, 'expressions that refer to functions get converted to pointers to those functions' Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7290 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>	2014-11-04 13:31:36 +01:00
Edward O'Callaghan	0625a8bcfb	{cpu,soc}: Use DEVICE_NOOP macro over dummy symbol Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>	2014-11-01 21:14:35 +01:00
Shawn Nematbakhsh	dd20d5d36c	baytrail: Remove unused devicetree fields We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit `4ab13fd3aa`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7218 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)	2014-10-28 18:08:43 +01:00
Shawn Nematbakhsh	b9590799b3	baytrail: gfx: Don't configure hotplug + backlight registers - The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `3f287cc31e`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-28 18:08:23 +01:00
Kein Yuan	787809e9ab	Baytrail/dptf: Always return 0 in TCPU._PPC According to DPTF team _PPC in TCPU must return 0 always. BUG=chromium:355964 TEST=Pass build. BRANCH=rambi Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73 Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/193069 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit `6dbcc677ce`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-28 18:01:36 +01:00
Aaron Durbin	1131889570	baytrail: handle MRC being an ELF file Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit `89c97d5e20`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7214 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)	2014-10-28 18:01:13 +01:00
Duncan Laurie	31ac9e3a9a	baytrail: Configure MSR for 2-core and 4-core P-state configutation Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit `8c8c0be000`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-28 17:57:12 +01:00
Aaron Durbin	89f5292ee6	baytrail: move cache-as-ram base address to 0xfe000000 Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit `73c07a319d`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-28 17:56:36 +01:00
Shawn Nematbakhsh	565d409753	baytrail: romstage: Add function to check SW WP status for vboot Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `5bba447654`) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 Reviewed-on: http://review.coreboot.org/7211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-28 17:56:11 +01:00
Isaac Christensen	d2044ccdc0	reg_script: default to n for ARCH_X86 The reg_script functionality is only used by specific chipsets so have it selected instead of defaulting to y for ARCH_X86. Change-Id: I8fb9466e148eed7896ca8ed80755c77ba1190583 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-10-22 03:57:51 +02:00
Tom Warren	64982c5002	tegra/nyan: sdram updates nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU Reviewed-on: https://chromium-review.googlesource.com/183939 (cherry picked from commit `a6df76afb5`) nyan_big: Add initial 792MHz BCT Reviewed-on: https://chromium-review.googlesource.com/183975 (cherry picked from commit `61d0122fdc`) nyan_big: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/184076 (cherry picked from commit `35e5c5e473`) tegra124: support tri-state Board Id Reviewed-on: https://chromium-review.googlesource.com/183855 (cherry picked from commit `1a9d1bd73a`) nyan: Fix SPI pinmux configuration Reviewed-on: https://chromium-review.googlesource.com/184281 (cherry picked from commit `ac4106b673`) nyan_big: Add 4GB 204/792MHz BCTs Reviewed-on: https://chromium-review.googlesource.com/184159 (cherry picked from commit `5ff002d09f`) tegra124: Add function for obtaining DRAM size via MC regs Reviewed-on: https://chromium-review.googlesource.com/184535 (cherry picked from commit `d4580c46de`) tegra124/nyan*: Obtain DRAM size dynamically Reviewed-on: https://chromium-review.googlesource.com/184431 (cherry picked from commit `a7db717447`) tegra124: Rearrange iRAM layout to allow more space for romstage Reviewed-on: https://chromium-review.googlesource.com/184240 (cherry picked from commit `6bdaabbc06`) tegra124: Fix MemoryType field name in SDRAM parameters. Reviewed-on: https://chromium-review.googlesource.com/185113 (cherry picked from commit `9caccd1e86`) nyan_big: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/183624 (cherry picked from commit `a1cbc00aa8`) tegra124: move FB_SIZE_MB to a more appropriate location Reviewed-on: https://chromium-review.googlesource.com/184930 (cherry picked from commit `ddea486fd4`) nyan: Initialize SDRAM without BootROM. Reviewed-on: https://chromium-review.googlesource.com/185114 (cherry picked from commit `1ff51b580b`) tegra124: Save SDRAM parameters to PMC registers for LP0 Reviewed-on: https://chromium-review.googlesource.com/182928 (cherry picked from commit `7476b4bd0e`) tegra124: Rewrite SDRAM parameter saving code to be more efficient Reviewed-on: https://chromium-review.googlesource.com/184388 (cherry picked from commit `25084bd040`) nyan: Slightly change the way SDRAM parameter files are set up Reviewed-on: https://chromium-review.googlesource.com/185286 (cherry picked from commit `a31887b804`) Squashed 16 commits for SDRAM support on nyan and nyan_big. Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6949 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:56:49 +02:00
Gabe Black	b3f08c61f1	cmos: Rename the CMOS related functions. Most of the code related to the mc146818 is not related to the RTC and is really for managing the CMOS storage. Since we intend to add a generic API for RTC drivers it's inconvenient for those functions to have an rtc_ prefix. This CL renames those functions so they start with cmos_ instead. There are some places where rtc_init was called with a comment that says something about starting the RTC. That wasn't correct before (the RTC is always running), but it looks a little odd now that the function is called cmos_init. This CL also opportunistically cleans up some style problems in this file. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/197794 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `9a9ad24888`) Removed the addition of stdint.h to mc146818rtc.h since types.h is now included. Changed rtc_init to cmos_init for fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex. Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>	2014-10-22 03:55:14 +02:00
Duncan Laurie	1b969f672e	broadwell: Update Haswell and Broadwell E0 microcode Broadwell D0 updated to 0x10 (debug) Broadwell E0 updated to 0xD Haswell updated to 0x1C Change-Id: Ib3e27b3467fec1106c69d82c0b1522d58025d67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/208212 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `048a8b68db`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-10-22 03:48:52 +02:00
Duncan Laurie	c09396785c	broadwell: Update microcode 40651: rev 00000018 306D3: rev FFFF000F 306D4: rev 00000009 Change-Id: I47a6caadc83f0ed96b0a4b0c624ad105d9dee3b6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `f8f0703c70`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:47:55 +02:00
Duncan Laurie	61680274c1	broadwell: ACPI, romstage, and other updates broadwell: Add romstage usbdebug support Reviewed-on: https://chromium-review.googlesource.com/199412 (cherry picked from commit `1050e7d3be`) broadwell: Add romstage code to configure PCH UART for console Reviewed-on: https://chromium-review.googlesource.com/199807 (cherry picked from commit `ecebda4eb5`) broadwell: Expand the PCI device convenience macros Reviewed-on: https://chromium-review.googlesource.com/199891 (cherry picked from commit `f8c54c70f1`) broadwell: Add ramstage driver for ADSP Reviewed-on: https://chromium-review.googlesource.com/199892 (cherry picked from commit `e8e986b0ba`) broadwell: Update ACPI devices Reviewed-on: https://chromium-review.googlesource.com/201080 (cherry picked from commit `2446b35578`) broadwell: Reserve DPR region Reviewed-on: https://chromium-review.googlesource.com/201081 (cherry picked from commit `8ecd9d2096`) broadwell: Remove old pei_data and add cpu function for romstage Reviewed-on: https://chromium-review.googlesource.com/201690 (cherry picked from commit `d206c9cdd6`) broadwell: Fixes for graphics without executing VBIOS Reviewed-on: https://chromium-review.googlesource.com/202356 (cherry picked from commit `0c031df1ce`) broadwell: Fix compilation failure when loglevel is lowered Reviewed-on: https://chromium-review.googlesource.com/202357 (cherry picked from commit `708ce78b2b`) broadwell: Disable GPIO controller interrupt Reviewed-on: https://chromium-review.googlesource.com/203645 (cherry picked from commit `2d17e98ede`) broadwell: Add support for E0 stepping Reviewed-on: https://chromium-review.googlesource.com/205160 (cherry picked from commit `802e9d3714`) broadwell: misc updates for CPU driver Reviewed-on: https://chromium-review.googlesource.com/205161 (cherry picked from commit `ea1d403817`) broadwell: Read power state earlier and store in romstage params Reviewed-on: https://chromium-review.googlesource.com/208151 (cherry picked from commit `b2198d7108`) broadwell: Add parameters to pei_data structure Reviewed-on: https://chromium-review.googlesource.com/208153 (cherry picked from commit `423fbf67e4`) broadwell: Move platform report output after power state is read Reviewed-on: https://chromium-review.googlesource.com/208213 (cherry picked from commit `acedf4146b`) Squashed 15 commits for broadwell support. Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6982 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:47:10 +02:00
Duncan Laurie	e256295218	broadwell: Update D0 microcode to FFFF000E New microcode released this week. Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `63ec6438b5`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6966 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:42:13 +02:00
Duncan Laurie	842bcd3c72	broadwell: Update microcode for supported CPUs This broadwell implementation will support Haswell ULT in addition to broadwell CPUs. Add the latest available microcode for the broadwell C0 and D0 parts as well as Haswell ULT. Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `69d5b7c834`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6965 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:41:14 +02:00
Duncan Laurie	c88c54c667	broadwell: add new intel SOC broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit `178400e570`) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit `30d3c25a0a`) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit `97a8d0b051`) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit `fa217361b2`) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit `bf8795ca92`) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit `099af14676`) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit `4f3c028686`) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit `10bad5bbb6`) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit `9c97532460`) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit `86ef1a45a2`) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit `f93b8bda71`) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit `8052030a9d`) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit `b35947d070`) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit `6ac4e56db6`) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit `2a25950670`) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit `01148cd2c9`) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit `31c91e811b`) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit `93dde85f98`) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit `9059b8e230`) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit `d83cc82c36`) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit `fc1e711290`) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit `26f437b27e`) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit `ea3cd39566`) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit `2c54df159b`) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit `34e4788955`) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit `bc0f7c6d2f`) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit `9951e79319`) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit `6d1efb94bd`) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit `abb5f87e54`) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit `a9c2d7ff3a`) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit `65ac1a07ab`) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit `17353803ba`) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit `49d7a023f3`) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit `17da652b44`) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit `4fce5fbb56`) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit `c6bf20309f`) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit `5082d4824d`) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit `ba0206ab76`) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit `d8fc9daf12`) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit `d355247333`) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit `d62cef1970`) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit `3b93b3ea79`) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit `68955ba4ff`) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit `b6fb672ae8`) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit `80ad8bb9bd`) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit `b4962acd70`) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit `8a457b8261`) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit `c220383c90`) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit `935404da11`) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit `6ae9d93c1a`) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit `28ffd71a41`) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit `781f3a1b72`) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit `a52d275e41`) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit `0678c739af`) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit `68b0122472`) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit `761cec3b6b`) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit `c2ea2d3a0c`) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit `4383de5846`) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit `0ef5961ebe`) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit `ffa5743f74`) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit `bb01deb8bb`) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit `3f25c23dc5`) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit `ddc4c116b4`) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit `8295e56c9b`) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit `28326aeaaf`) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit `749988fff0`) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit `198a3cd5cb`) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit `8159689bba`) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit `e2ab52340e`) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit `c7a8c86710`) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit `abb99b36e9`) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit `e09a1f8520`) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit `7e58f43e46`) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit `68b1f70e32`) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit `49088b312b`) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit `344c3c511d`) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit `ea8f97738e`) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit `8c99038a5c`) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:36:44 +02:00
Duncan Laurie	f0aaa29989	baytrail: Move HDA verb table to Intel SOC common directory This is common code for Intel SOC that can be shared. Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `3a9057b961`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:35:13 +02:00
Duncan Laurie	d8c4f2b724	baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `f9919e2551`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:33:20 +02:00
Kein Yuan	3511023f34	baytrail/rambi: S3 support and other updates baytrail: Change all GPIO related pull resistors from 10K to 20K Reviewed-on: https://chromium-review.googlesource.com/187570 (cherry picked from commit `762e99861d`) baytrail: workaround kernel using serial console on resume Reviewed-on: https://chromium-review.googlesource.com/188011 (cherry picked from commit `b0da3bdb5b`) baytrail: allow dirty cache line evictions for SMRAM to stick Reviewed-on: https://chromium-review.googlesource.com/188015 (cherry picked from commit `50fb1e6a84`) baytrail: Optionally pull up TDO and TMS to avoid power loss in S3. Reviewed-on: https://chromium-review.googlesource.com/188260 (cherry picked from commit `e240856609`) rambi: always load option rom Reviewed-on: https://chromium-review.googlesource.com/188721 (cherry picked from commit `d8a1d10854`) baytrail: use new chromeos ram oops API Reviewed-on: https://chromium-review.googlesource.com/186394 (cherry picked from commit `f38e6969df`) rambi: always show dev/rec screens on eDP connected panel Reviewed-on: https://chromium-review.googlesource.com/188731 (cherry picked from commit `7d8570ac52`) baytrail: stop e820 reserving default SMM region Reviewed-on: https://chromium-review.googlesource.com/189084 (cherry picked from commit `6fce823512`) baytrai: update MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/189196 (cherry picked from commit `36b33a25b6`) rambi: Put LPE device into ACPI mode Reviewed-on: https://chromium-review.googlesource.com/189371 (cherry picked from commit `5955350cd5`) baytrail: DPTF: Enable mainboard-specific PPCC Reviewed-on: https://chromium-review.googlesource.com/189576 (cherry picked from commit `27fae3e670`) baytrail: Add config option for PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189994 (cherry picked from commit `1cc31a7c02`) rambi: Enable PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189995 (cherry picked from commit `c98ae1fee5`) Squashed 13 commits for baytrail/rambi. Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6957 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-22 03:22:25 +02:00
Kyösti Mälkki	1729cd8574	x86 romstage: Move stack just below RAMTOP Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>	2014-10-19 06:14:05 +02:00
Kyösti Mälkki	d05d0db0d0	haswell baytrail: Enable RELOCATABLE_RAMSTAGE Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>	2014-10-19 06:13:35 +02:00
Ronald G. Minnich	2adb297cf9	uarts: 32/64 cleanup We had lots of casts that caused warnings when compiling on RISCV. Clean them up. Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7066 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>	2014-10-16 17:41:14 +02:00
Scott Radcliffe	8ffc085e1a	intel/fsp_baytrail: Add padding so device_nvs location matches ACPI The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-14 18:59:22 +02:00
Scott Radcliffe	bf9d6a8567	baytrail: Add padding to the end of device_nvs to match ACPI ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7039 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-14 18:59:07 +02:00
Scott Radcliffe	375e6ce4ae	intel/fsp_baytrail: Clear the GNVS area prior to filling Zero out the GNVS area so that uninitialized portions are defined. Tests using Microsoft Windows (XP/7/8) gave a bluescreen bugcheck: A5 (ACPI_BIOS_ERROR) with the first parameter (0x00001000) (ACPI_BIOS_USING_OS_MEMORY). Some ACPI enumerated devices use the GNVS area to define whether they're enabled and their MMIO regions. On my custom baytrail-based board and build, these devices were disabled but GNVS had uninitialized data indicating the devices were enabled with improper MMIO regions. Should investigate further to see where the GNVS device values are set if enabled and make sure they're set to valid values even when the devices are disabled via the mainboard/devicetree.cb. Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>	2014-10-14 18:58:46 +02:00
Kayalvizhi Dhandapani	762d53d418	intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route" Fix the error 'implicit declaration of function "southcluster_smm_save_gpio_route"', when SMM module is added. Change-Id: Ia050ab7e2b036541537b645d3fe4dc747cd1dff8 Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7024 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>	2014-10-09 22:09:51 +02:00
Kayalvizhi Dhandapani	a16055ae8a	intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module added Change-Id: I6d8622c7f343619b915442d8056aa6672dfc4f6e Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7025 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>	2014-10-09 22:09:25 +02:00
Kayalvizhi Dhandapani	454625c5cf	intel/fsp_baytrail: Fix SMM/SMI With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit `3eb8eb7eba` Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)	2014-10-09 21:59:45 +02:00
Shawn Nematbakhsh	e87ee14449	baytrail: update C0 microcode baytrail: Add 811 microcode for C0 parts Incorporate 811 microcode version for C0 stepping parts. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d Reviewed-on: https://chromium-review.googlesource.com/191693 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `57c9cbdb9e`) baytrail: Add 813 microcode for C0 parts Incorporate 813 microcode version for C0 stepping parts. Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `bf15a48c6b`) baytrail: Update microcode to version 816 Version 816 of microcode. Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364 Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit `16512b09e3`) Squashed 3 successive updates for baytrail C0 microcode. Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-10-01 23:30:05 +02:00
Mohan D'Costa	ed0c83877f	intel/fsp_baytrail: Add S3 suspend/resume Support This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)	2014-09-29 19:35:57 +02:00
Furquan Shaikh	7657057892	soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit `e71d45733d`) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad@quicinc.com> (cherry picked from commit `e6e12c39ef`) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6963 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)	2014-09-25 19:05:46 +02:00
Aaron Durbin	cd0f2283e8	baytrail: add 80c microcode for C0 parts Incoprorate 80c microcode version for C0 stepping parts. Change-Id: I2a76b4c92cac0aca5949313060f1d315ebd8e1a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187842 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit `318027a885`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>	2014-09-24 17:42:13 +02:00
Andrew Bresticker	24d4f7f8de	tegra124/nyan: memory and display updates tegra124: use pll_c_out1 as sclk parent Reviewed-on: https://chromium-review.googlesource.com/180865 (cherry picked from commit `418337a5bd`) tegra124: take LP cluster out of reset Reviewed-on: https://chromium-review.googlesource.com/180866 (cherry picked from commit `74cdc68ea9`) tegra124: norrin: display code clean up Reviewed-on: https://chromium-review.googlesource.com/181003 (cherry picked from commit `63843ec61b`) tegra124: Change the display hack to use window A Reviewed-on: https://chromium-review.googlesource.com/182001 (cherry picked from commit `ef245e42eb`) tegra124: norrin: Initialize frame buffer Reviewed-on: https://chromium-review.googlesource.com/182090 (cherry picked from commit `b7c1d1b3c9`) nyan: do not enable pull-ups on SPI1 (EC) data pins Reviewed-on: https://chromium-review.googlesource.com/181063 (cherry picked from commit `2f55188501`) tegra124: Add source for the LP0 resume blob. Reviewed-on: https://chromium-review.googlesource.com/183152 (cherry picked from commit `a00d099bf7`) tegra124: Revise Memory Controller registers structure definition. Reviewed-on: https://chromium-review.googlesource.com/182992 (cherry picked from commit `ae83564cdd`) tegra124: Add more PMC register details. Reviewed-on: https://chromium-review.googlesource.com/183231 (cherry picked from commit `d62ed2c196`) tegra124: Add SDRAM configuration header file from cbootimage. Reviewed-on: https://chromium-review.googlesource.com/182613 (cherry picked from commit `193ed2a104`) tegra124: Revise sdram_param.h for Coreboot. Reviewed-on: https://chromium-review.googlesource.com/182614 (cherry picked from commit `311b0568c5`) tegra124: Fix EMC base address. Reviewed-on: https://chromium-review.googlesource.com/183602 (cherry picked from commit `587c896929`) tegra124: Add EMC registers definition. Reviewed-on: https://chromium-review.googlesource.com/183622 (cherry picked from commit `67a8e5c7e8`) tegra124: Never touch MEM(MC)/EMC clocks in ramstage. Reviewed-on: https://chromium-review.googlesource.com/183623 (cherry picked from commit `8e3bb34d4a`) tegra124: use RAM_CODE[3:2] for ram code Reviewed-on: https://chromium-review.googlesource.com/183833 (cherry picked from commit `0154239467`) tegra124: Allow setting PLLM (clock for SDRAM). Reviewed-on: https://chromium-review.googlesource.com/183621 (cherry picked from commit `a534e5b7c6`) tegra124: SDRAM Initialization. Reviewed-on: https://chromium-review.googlesource.com/182615 (cherry picked from commit `5a60ae93b0`) tegra124: Get RAM_CODE for SDRAM initialization. Reviewed-on: https://chromium-review.googlesource.com/183781 (cherry picked from commit `a5b7ce7052`) Squashed 18 nyan/tegra commits for memory and display. Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6914 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)	2014-09-22 19:00:19 +02:00
Julius Werner	64b9ca9d4e	arm: Move libgcc assembly macros to arch/asm.h libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182178 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit `a780670def`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6917 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>	2014-09-22 18:46:57 +02:00
Julius Werner	03784fa97a	Add check_member macro to allow clean and easy struct offset checking This patch adds a new static assertion macro that can be used to check the offsets in structures that overlay register sets at compile time. It uses the _Static_assert() declaration from the new ISO C11 standard, which is supported (even without -std=c11) by GCC after version 4.6. (There is supposedly also support in clang, although I haven't tried it... let's deal with compiler issues when/if they turn up.) I've added it to all structures for our current ARM SoCs for now, and I think every new register overlay we add going forward should use them (at least for the last member, but feel free to add more if you think it's useful). Change-Id: If32510e7049739ad05618d363a854dc372d64386 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit `cef5fa13c3`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6905 Tested-by: build bot (Jenkins)	2014-09-22 18:42:20 +02:00
Aaron Durbin	4177db52a2	baytrail/rambi: spi, charger, and audio updates baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit `4e7f0e8ae1`) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit `82cce4d2b4`) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit `1b50affb1f`) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit `6eff475dae`) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit `9fc310d7e2`) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit `940a0fa4df`) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit `334f2a5c7c`) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit `696ece68cb`) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit `1d9ba15858`) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit `9d6056dd70`) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit `c64627689b`) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit `287e893661`) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit `2f62a11927`) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit `962a79ef72`) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit `b5e10ad47b`) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit `8c1a62f1f4`) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit `b9329126ca`) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit `ba44e2e04f`) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit `76b25df5a3`) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit `5192e2464f`) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit `8d1ab5de1d`) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit `c19c0f1d7c`) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit `5412ac5c07`) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit `932a5a3803`) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit `f64cb1ae77`) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>	2014-09-19 21:38:48 +02:00
Isaac Christensen	0c0efa7e50	exynos5250: remove unused ret variable in cpu.c Showed up as an error when '--gc-sections' was added as a flag to the compiler. Change-Id: I214d3e16a72fca0becc677d7af66097464d64247 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>	2014-09-19 21:37:56 +02:00
Shawn Nematbakhsh	51d787a5cf	rambi/baytrail: ACPI, GPIO, audio, misc updates rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit `8afd981a09`) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit `1b80d71e49`) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit `87d49323ca`) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit `1b520b577f`) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit `8ed0ef4c3b`) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit `969dffda1d`) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit `a6b85ad950`) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit `95a79aff57`) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit `8ad02684b2`) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit `c92db75de5`) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit `821ce0e72c`) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit `f99804c264`) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit `753fadb6b9`) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit `78775098a8`) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit `3022c82b02`) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit `398387ed75`) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit `edde584bb2`) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit `1d6aeb85fd`) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit `e9c002c393`) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit `e04c20962a`) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit `dda4687931`) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit `0457b5dce1`) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit `0472e6bd45`) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit `52bec10986`) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit `3931987050`) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit `44558c3346`) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit `ee4620a90a`) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit `ffb73af007`) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>	2014-09-18 01:23:14 +02:00
David Hendricks	1101a71219	spi: add Kconfig variable for dual-output read enable Add a Kconfig variable so that driver code knows whether or not to use dual-output reads. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5 Reviewed-on: https://chromium-review.googlesource.com/177834 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit `de6869a335`) tegra124: implement x2 mode for SPI transfers on CBFS media This implements x2 mode when reading CBFS media over SPI. In theory this effectively doubles our throughput, though the initial results were almost negligibly better. Using a logic analyzer we see a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we want to see further gains here then we'll probably need to tune AHB arbitration and utilization to eliminate bubbles/stalls when copying from APB DMA. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e Reviewed-on: https://chromium-review.googlesource.com/177835 Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit `2928922336`) nyan: turn on dual-output reads for SPI flash Nyan's SPI chip is capable of dual-output reads, so let's use it. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df Reviewed-on: https://chromium-review.googlesource.com/177836 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit `62de0889a9`) Squashed three commits to enable dual output spi reads for nyan. Also fixed the spi_xfer interface that has been updated to use bytes instead of bits. Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6909 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>	2014-09-17 19:56:16 +02:00
Julius Werner	04b01893a9	exynos5250: Fix PMU register address map Patch `12b121f3fe` introduced an off-by-one error in the offsets of the PMU register struct, which put both the newly added register and the PSHOLD that comes after it in the wrong place. This patch corrects the offsets (5420 had already been correct). Change-Id: I1d9d31a6a73ee91890824e94fbd247d5feb4f6ae Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179411 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `5fdc74bc18`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>	2014-09-15 18:59:36 +02:00
Julius Werner	85620db107	arm: Move exception_init() close to console_init() This patch adds stub implementations of exception_init() to all archs so that it can be called from src/lib/hardwaremain.c. It also moves/adds all other invocations of exception_init() (which needs to be rerun in every stage) close to console_init(), in the hopes that it will be less likely overlooked when creating future boards. Also added (an ineffective) one to the armv4 bootblock implementations for consistency and in case we want to implement it later. Change-Id: Iecad10172d25f6c1fc54b0fec8165d7ef60e3414 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176764 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit `2960623f4a`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6884 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)	2014-09-13 02:21:02 +02:00
Julius Werner	edf6b57f73	tegra124/nyan: display, clock, and other updates tegra124: Set Tx FIFO threshold value to recommended setting Reviewed-on: https://chromium-review.googlesource.com/175200 (cherry picked from commit `c8f086711c`) tegra124: add CLK_X definitions Reviewed-on: https://chromium-review.googlesource.com/175220 (cherry picked from commit `3f8a844bd2`) tegra124: fix incorrect struct member in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/175270 (cherry picked from commit `967193d598`) tegra124: add the _x clocks to clock_enable_clear_reset Reviewed-on: https://chromium-review.googlesource.com/175539 (cherry picked from commit `df4c515d73`) tegra124: add clock support code for graphics. Reviewed-on: https://chromium-review.googlesource.com/175162 (cherry picked from commit `b8eb6ab4cd`) tegra124: Clean up some #defines for DMA Reviewed-on: https://chromium-review.googlesource.com/175631 (cherry picked from commit `1a0a900f2d`) tegra124: enable flow control for APBDMA in SPI driver Reviewed-on: https://chromium-review.googlesource.com/175630 (cherry picked from commit `873e6f9e95`) nyan: move clock setup for the display out of dca_init Reviewed-on: https://chromium-review.googlesource.com/175656 (cherry picked from commit `32dd9947a6`) tegra124: more display PLL setup and clock hardcode removal. Reviewed-on: https://chromium-review.googlesource.com/175732 (cherry picked from commit `80402876b5`) tegra124: move dp.c from tegra to tegra124 Reviewed-on: https://chromium-review.googlesource.com/175830 (cherry picked from commit `e98be569b0`) tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb Reviewed-on: https://chromium-review.googlesource.com/175889 (cherry picked from commit `4e513196b0`) tegra: get rid of struct members that are not used Reviewed-on: https://chromium-review.googlesource.com/176023 (cherry picked from commit `032b8a0c9f`) tegra124: Increase SCLK (AVP) to 300MHz Reviewed-on: https://chromium-review.googlesource.com/175489 (cherry picked from commit `7e082f2c2f`) tegra124: Address old main CPU starting review feedback. Reviewed-on: https://chromium-review.googlesource.com/175933 (cherry picked from commit `1d76ac71bd`) tegra124: Revise clock source configuration for irregular peripherals. Reviewed-on: https://chromium-review.googlesource.com/176109 (cherry picked from commit `1021c21519`) nyan: add timestamps in romstage Reviewed-on: https://chromium-review.googlesource.com/176172 (cherry picked from commit `cd626aa10b`) tegra124: Allow enabling clock output for external peripherals. Reviewed-on: https://chromium-review.googlesource.com/176108 (cherry picked from commit `ea9fb6393e`) nyan: Enable and configure clocks for I2S and audio codec. Reviewed-on: https://chromium-review.googlesource.com/176104 (cherry picked from commit `1fb659b3e7`) tegra124: Fix typo in pinmux name. Reviewed-on: https://chromium-review.googlesource.com/176215 (cherry picked from commit `c7915ad41a`) nyan: Add pinmux settings for audio peripherals. Reviewed-on: https://chromium-review.googlesource.com/176212 (cherry picked from commit `37412f3201`) nyan: De-array-ify the PMIC setup code. Reviewed-on: https://chromium-review.googlesource.com/176903 (cherry picked from commit `86ab1ce9fb`) nyan: Add a kconfig for building for the original nyans in pixel cases. Reviewed-on: https://chromium-review.googlesource.com/176904 (cherry picked from commit `1d05fd5bc4`) nyan: Set the CPU voltage differently depending on which PMIC is in use. Reviewed-on: https://chromium-review.googlesource.com/176905 (cherry picked from commit `31507f6a57`) nyan: Increase the CPU voltage to 1.2V. Reviewed-on: https://chromium-review.googlesource.com/176906 (cherry picked from commit `fe4795e66b`) tegra124: Flesh out/tidy up the flow controller constants. Reviewed-on: https://chromium-review.googlesource.com/177085 (cherry picked from commit `b50d315506`) tegra124: When leaving the bootblock/AVP, really stop the AVP. Reviewed-on: https://chromium-review.googlesource.com/177086 (cherry picked from commit `06c10df889`) nyan: Set SPI4 speed to 33MHz Reviewed-on: https://chromium-review.googlesource.com/177038 (cherry picked from commit `c98de65482`) nyan: Do console_init() in romstage Reviewed-on: https://chromium-review.googlesource.com/176763 (cherry picked from commit `0bec32e09e`) nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option. Reviewed-on: https://chromium-review.googlesource.com/177486 (cherry picked from commit `7cbb801d00`) nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin. Reviewed-on: https://chromium-review.googlesource.com/177487 (cherry picked from commit `6b119685f6`) tegra124: Bump up HCLK and PCLK Reviewed-on: https://chromium-review.googlesource.com/177563 (cherry picked from commit `c25337dac8`) nyan: Add some code for reading the board ID. Reviewed-on: https://chromium-review.googlesource.com/177488 (cherry picked from commit `5fccbce99e`) nyan: Use the board ID to decide how to initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/177489 (cherry picked from commit `677bdb9df5`) nyan: Create kconfig variables for each SDRAM config. Reviewed-on: https://chromium-review.googlesource.com/177580 (cherry picked from commit `d7ddcf262a`) tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line. Reviewed-on: https://chromium-review.googlesource.com/177637 (cherry picked from commit `bd533cc109`) tegra124: Initialize the MCR when setting up the UART. Reviewed-on: https://chromium-review.googlesource.com/177638 (cherry picked from commit `38c84786fc`) tegra124: fix SPI AHB burst length Reviewed-on: https://chromium-review.googlesource.com/177564 (cherry picked from commit `f292352632`) tegra124: remove unneeded debug print in SPI code Reviewed-on: https://chromium-review.googlesource.com/177833 (cherry picked from commit `34a5004026`) nyan: Set up the SOC and TPM reset pin. Reviewed-on: https://chromium-review.googlesource.com/177965 (cherry picked from commit `b81a5bd15a`) tegra124: Allow some time for packets to appear in Rx FIFO Reviewed-on: https://chromium-review.googlesource.com/177832 (cherry picked from commit `8f70a25b1e`) nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722 Reviewed-on: https://chromium-review.googlesource.com/178226 (cherry picked from commit `c536b0d82f`) nyan: change devicetree for the new display settings. Reviewed-on: https://chromium-review.googlesource.com/177958 (cherry picked from commit `43abed730f`) nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs Reviewed-on: https://chromium-review.googlesource.com/178914 (cherry picked from commit `e47b6a609b`) Tegra124: nyan: Disable VPR Reviewed-on: https://chromium-review.googlesource.com/179327 (cherry picked from commit `441aa27644`) tegra124: norrin: fix display issue Reviewed-on: https://chromium-review.googlesource.com/179745 (cherry picked from commit `c1c1ae69f6`) tegra124: Add iRAM layout information. Reviewed-on: https://chromium-review.googlesource.com/179814 (cherry picked from commit `d00f135c93`) tegra124: Run bootblock and ROM stage out of DRAM. Reviewed-on: https://chromium-review.googlesource.com/179822 (cherry picked from commit `2d3ec06ec3`) nyan: clean up a comment regarding video Reviewed-on: https://chromium-review.googlesource.com/180161 (cherry picked from commit `03b5e88a66`) tegra124: norrin: the first step to clean up display code Reviewed-on: https://chromium-review.googlesource.com/180135 (cherry picked from commit `9d0c12dfef`) Squashed 49 commits for tegra124/nyan. Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>	2014-09-13 02:00:03 +02:00
Hung-Te Lin	2fc3b6281f	tegra124/nyan: various fixes and additions Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit `d3157e9a38`) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit `55af9a86a5`) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit `9d917927a5`) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit `36e9370f30`) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit `fba4ae1080`) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit `12649c9611`) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit `eed380e090`) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit `ea81cb44a1`) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit `72365c3369`) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit `3f31a634f6`) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit `bc1c289268`) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit `7706f3200f`) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit `9513e608f3`) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit `25a91fcf7e`) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit `581f592c12`) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit `5ab100b0ba`) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit `822cad0cee`) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit `c0e22d76d3`) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit `dad7f68c76`) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit `81b977a275`) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit `51c9a34240`) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit `36760a4463`) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit `e24773eb94`) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit `88354b9964`) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit `29173ba586`) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit `1d1630e770`) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit `3eebd10afe`) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit `74512b7ecf`) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit `7e944208a1`) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit `c66e228592`) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit `6dbb4e5f0d`) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit `ecd5c398ff`) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit `73fcc4981d`) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit `7256aba07e`) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6870 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)	2014-09-12 21:59:45 +02:00
Gabe Black	d40be1107c	tegra124/nyan: rougly stable code base nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit `3697b6454c`) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit `3a0cd48a0d`) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit `a83d065d66`) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit `ea703137fc`) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit `9c10a3074e`) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit `f6be8b0e60`) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit `4dd5f1f091`) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit `61bedbf0f8`) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit `94550fdfa5`) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit `e95ccd984f`) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit `7c5169a197`) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit `130a07c86d`) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit `da808e4691`) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit `9305ff0696`) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit `4d2a5a56b9`) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit `5f861f13c7`) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit `e142b9572a`) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit `b6e1a70103`) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit `af49a5bd1f`) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit `87687633a2`) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit `c107eaca3d`) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit `1e2f9fd442`) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit `f9dc2a8d80`) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit `97e61f36ad`) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit `750c0a5d69`) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit `651c7ab96b`) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit `4a9b7b47b3`) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit `c056fa954e`) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit `c1a321c8f6`) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit `c026a3fb86`) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit `7d79d7dd9f`) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit `ff172bfe30`) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit `8bc527aa4a`) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit `86a6423b66`) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit `4c394dfbce`) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit `2845a44871`) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit `c238b87bcd`) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit `f415d2c0aa`) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit `f1930faea3`) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit `bc2ba9c15c`) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit `19dd9c85e4`) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit `3362cf3a7d`) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit `08626ffac4`) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit `a2df8f3a9c`) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit `6727f65702`) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit `9387b02dff`) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit `924f61ea89`) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit `8d9387432f`) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit `f6a5f5c456`) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>	2014-09-11 23:13:52 +02:00
Gabe Black	8932f11c91	tegra124: Make tegra124 compilable with serial turned off. The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `a4f2dd4902`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-09-10 19:42:41 +02:00
Gabe Black	58f3062580	nyan: Use the new pinmux functions as part of UART setup. The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `d29e655b68`) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `4c6dd4c7ca`) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6861 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>	2014-09-10 19:41:32 +02:00
Gabe Black	dda0e66d9c	Exynos5420: Fix up the i2c driver for use with the TPM driver The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit `cf68626942`) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>	2014-09-10 19:39:43 +02:00
Isaac Christensen	3a92be72f8	nvidia-cbootimage: integrate into coreboot make Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6851 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>	2014-09-10 19:34:43 +02:00

1 2 3 4 5

239 commits