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nyan: De-array-ify the PMIC setup code.

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We're going to need some logic to decide what to set the PMIC registers to, so
we need to set the registers using code instead of an array. I never really
liked the array way of doing things anyway.

BUG=None
TEST=With this and other changes, built and booted on the new and old nyan
boards.
BRANCH=None

Change-Id: Ice7ee2830b1b24c25ac506ee004574eb861cf1c0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176903
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-11-14 13:42:25 -08:00 • committed by chrome-internal-fetch
commit 86ab1ce9fb
1 changed files with 20 additions and 33 deletions
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53
src/mainboard/google/nyan/pmic.c
View file

@ -25,34 +25,32 @@
#include "pmic.h"
struct pmic_write
{
uint8_t reg; // Register to write.
uint8_t val; // Value to write.
};
enum {
AS3722_I2C_ADDR = 0x40
};
static struct pmic_write pmic_writes[] =
static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
{
/* Don't need to set up VDD_CORE - already done - by OTP */
i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
udelay(10 * 1000);
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
{ 0x00, 0x28 },
/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
pmic_write_reg(bus, 0x00, 0x28);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
{ 0x06, 0x28 },
/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
pmic_write_reg(bus, 0x06, 0x28);
/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
{ 0x12, 0x10 },
/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
pmic_write_reg(bus, 0x12, 0x10);
/*
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
@ -61,23 +59,12 @@ static struct pmic_write pmic_writes[] =
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
{ 0x16, 0x3f },
pmic_write_reg(bus, 0x16, 0x3f);
/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
/* panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
{ 0x0c, 0x07 },
{ 0x20, 0x10 },
};
void pmic_init(unsigned bus)
{
int i;
for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
&pmic_writes[i].val, 1);
udelay(10 * 1000);
}
pmic_write_reg(bus, 0x0c, 0x07);
pmic_write_reg(bus, 0x20, 0x10);
}