broadwell: Clean up and expand report_platform
- Use the CPUID defines to print CPU variant and stepping information at boot. - Use the LPC Device ID defines to print the PCH variant at boot. - Use the IGD Device ID defines to print the GT SKU at boot. - Move report_memory_config() into romstage/report_platform.c BUG=chrome-os-partner:28234 TEST=None Change-Id: I199abdf01ed570055a1933065a8e0d7f4799fcd8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198924 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
c6bf20309f
commit
5082d4824d
2 changed files with 136 additions and 83 deletions
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@ -94,49 +94,6 @@ static const char* ecc_decoder[] = {
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};
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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static void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
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i, ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n",
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ecc_decoder[(ch_conf >> 24) & 3]);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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/**
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* Find PEI executable in coreboot filesystem and execute it.
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*
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* @param pei_data: configuration data for UEFI PEI reference code
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@ -17,13 +17,65 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/cpu.h>
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#include <string.h>
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#include "southbridge/intel/lynxpoint/pch.h"
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/x86/msr.h>
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#include "haswell.h"
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#include <broadwell/cpu.h>
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#include <broadwell/pch.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/romstage.h>
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#include <broadwell/systemagent.h>
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static struct {
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u32 cpuid;
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const char *name;
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} cpu_table [] = {
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{ CPUID_HASWELL_A0, "Haswell A0" },
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{ CPUID_HASWELL_B0, "Haswell B0" },
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{ CPUID_HASWELL_C0, "Haswell C0" },
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{ CPUID_HASWELL_ULT_B0, "Haswell ULT B0" },
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{ CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" },
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{ CPUID_HASWELL_HALO, "Haswell Perf Halo" },
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{ CPUID_BROADWELL_C0, "Broadwell C0" },
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{ CPUID_BROADWELL_D0, "Broadwell D0" },
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};
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static struct {
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u16 lpcid;
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const char *name;
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} pch_table [] = {
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{ PCH_LPT_LP_SAMPLE, "LynxPoint LP Sample" },
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{ PCH_LPT_LP_PREMIUM, "LynxPoint LP Premium" },
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{ PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" },
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{ PCH_LPT_LP_VALUE, "LynxPoint LP Value" },
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{ PCH_WPT_HSW_U_SAMPLE, "Haswell U Sample" },
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{ PCH_WPT_BDW_U_SAMPLE, "Broadwell U Sample" },
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{ PCH_WPT_BDW_U_PREMIUM, "Broadwell U Premium" },
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{ PCH_WPT_BDW_U_BASE, "Broadwell U Base" },
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{ PCH_WPT_BDW_Y_SAMPLE, "Broadwell Y Sample" },
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{ PCH_WPT_BDW_Y_PREMIUM, "Broadwell Y Premium" },
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{ PCH_WPT_BDW_Y_BASE, "Broadwell Y Base" },
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{ PCH_WPT_BDW_H, "Broadwell H" },
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};
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static struct {
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u16 igdid;
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const char *name;
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} igd_table [] = {
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{ IGD_HASWELL_ULT_GT1, "Haswell ULT GT1" },
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{ IGD_HASWELL_ULT_GT2, "Haswell ULT GT2" },
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{ IGD_HASWELL_ULT_GT3, "Haswell ULT GT3" },
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{ IGD_BROADWELL_U_GT1, "Broadwell U GT1" },
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{ IGD_BROADWELL_U_GT2, "Broadwell U GT2" },
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{ IGD_BROADWELL_U_GT3_15W, "Broadwell U GT3 (15W)" },
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{ IGD_BROADWELL_U_GT3_28W, "Broadwell U GT3 (28W)" },
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{ IGD_BROADWELL_Y_GT2, "Broadwell Y GT2" },
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{ IGD_BROADWELL_H_GT2, "Broadwell U GT2" },
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{ IGD_BROADWELL_H_GT3, "Broadwell U GT3" },
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};
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static void report_cpu_info(void)
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{
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@ -33,6 +85,7 @@ static void report_cpu_info(void)
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int vt, txt, aes;
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msr_t microcode_ver;
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const char *mode[] = {"NOT ", ""};
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const char *cpu_type = "Unknown";
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index = 0x80000000;
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cpuidr = cpuid(index);
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@ -57,59 +110,102 @@ static void report_cpu_info(void)
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wrmsr(0x8B, microcode_ver);
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cpuidr = cpuid(1);
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microcode_ver = rdmsr(0x8b);
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printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
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/* Look for string to match the name */
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for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
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if (cpu_table[i].cpuid == cpuidr.eax) {
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cpu_type = cpu_table[i].name;
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break;
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}
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}
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printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
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printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
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cpuidr.eax, cpu_type, microcode_ver.hi);
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aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
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txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
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vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
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printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
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mode[aes], mode[txt], mode[vt]);
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printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
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"VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
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}
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/* The PCI id name match comes from Intel document 472178 */
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static struct {
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u16 dev_id;
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const char *dev_name;
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} pch_table [] = {
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{0x8c41, "Mobile Engineering Sample"},
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{0x8c42, "Desktop Engineering Sample"},
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{0x8c44, "Z87"},
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{0x8c46, "Z85"},
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{0x8c49, "HM86"},
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{0x8c4a, "H87"},
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{0x8c4b, "HM87"},
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{0x8c4c, "Q85"},
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{0x8c4e, "Q87"},
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{0x8c4f, "QM87"},
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{0x8c50, "B85"},
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{0x8c52, "C222"},
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{0x8c54, "C224"},
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{0x8c56, "C226"},
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{0x8c5c, "H81"},
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{0x9c41, "LP Full Featured Engineering Sample"},
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{0x9c43, "LP Premium"},
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{0x9c45, "LP Mainstream"},
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{0x9c47, "LP Value"},
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};
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static void report_pch_info(void)
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{
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int i;
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u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
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u16 lpcid = pch_type();
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const char *pch_type = "Unknown";
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for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
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if (pch_table[i].dev_id == dev_id) {
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pch_type = pch_table[i].dev_name;
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if (pch_table[i].lpcid == lpcid) {
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pch_type = pch_table[i].name;
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break;
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}
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}
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printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
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pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));
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printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
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lpcid, pch_revision(), pch_type);
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}
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static void report_igd_info(void)
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{
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int i;
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u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID);
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const char *igd_type = "Unknown";
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for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
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if (igd_table[i].igdid == igdid) {
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igd_type = igd_table[i].name;
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break;
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}
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}
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printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
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igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type);
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}
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void report_platform_info(void)
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{
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report_cpu_info();
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report_pch_info();
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report_igd_info();
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}
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
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i, ch_conf);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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