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tegra124: Bump up HCLK and PCLK

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This sets the sclk:hclk:pclk ratio to 1:2:2 which allows faster
transfers from peripherals to memory.

Performance-wise this currently decreases ramstage loading time
by about 20ms and payload loading time by 35ms.

BUG=chrome-os-partner:24182
BRANCH=none
TEST=Built and booted on Nyan rev 1 and 0. No longer see long
delays in between bytes when transferring >64 bytes via SPI.
CQ-DEPEND=CL:177578

Change-Id: I5812122bf6312a1ab490945c6e52fa3372e86fc9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177563
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
David Hendricks 2013-11-21 17:03:51 -08:00 • committed by chrome-internal-fetch
commit c25337dac8
1 changed files with 4 additions and 3 deletions
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7
src/soc/nvidia/tegra124/clock.c
View file

@ -395,9 +395,10 @@ void clock_init(void)
setbits_le32(&clk_rst->pllc_misc, PLLC_MISC_LOCK_ENABLE);
while (!(read32(&clk_rst->pllc_base) & PLL_BASE_LOCK)) /* wait */;
/* APB pclk and AHB hclk derive from sclk, let's not overkill them */
write32(3 << HCLK_DIVISOR_SHIFT | 3 << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate); /* pclk = hclk/4 = sclk/16 */
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */
write32(0 << SCLK_DIVIDEND_SHIFT |
(div_round_up(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT
| SCLK_DIV_ENB, &clk_rst->super_sclk_div);