broadwell: pch.h: split PM into new header
Various register/bit defines for power management offsets in PMBASE are split into a separate header together with the prototypes for pmutil helper functions. BUG=chrome-os-partner:28234 TEST=None Change-Id: I3d79e288b79641d8c4b4c8d10ed122b0c5c7e143 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198427 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
30d3c25a0a
commit
97a8d0b051
2 changed files with 168 additions and 112 deletions
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@ -143,30 +143,6 @@ int pch_is_lp(void);
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u16 get_pmbase(void);
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u16 get_gpiobase(void);
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/* Power Management register handling in pmutil.c */
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/* PM1_CNT */
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void enable_pm1_control(u32 mask);
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void disable_pm1_control(u32 mask);
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/* PM1 */
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u16 clear_pm1_status(void);
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void enable_pm1(u16 events);
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u32 clear_smi_status(void);
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/* SMI */
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void enable_smi(u32 mask);
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void disable_smi(u32 mask);
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/* ALT_GP_SMI */
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u32 clear_alt_smi_status(void);
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void enable_alt_smi(u32 mask);
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/* TCO */
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u32 clear_tco_status(void);
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void enable_tco_sci(void);
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/* GPE0 */
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u32 clear_gpe_status(void);
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void clear_gpe_enable(void);
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void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
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void disable_all_gpe(void);
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void enable_gpe(u32 mask);
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void disable_gpe(u32 mask);
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/*
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* get GPIO pin value
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*/
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@ -217,9 +193,6 @@ void pch_enable_lpc(void);
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#endif /* !__PRE_RAM__ && !__SMM__ */
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#endif /* __ASSEMBLER__ */
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
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@ -693,91 +666,6 @@ void pch_enable_lpc(void);
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define PROC_CNT 0x10
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#define LV2 0x14
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#define LV3 0x15
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#define LV4 0x16
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#define PM2_CNT 0x50 // mobile only
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#define GPE0_STS 0x20
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#define PME_B0_STS (1 << 13)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define RI_STS (1 << 8)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_STS_2 0x24
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#define GPE0_EN 0x28
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define TCOSCI_EN (1 << 6)
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#define GPE0_EN_2 0x2c
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#define SMI_EN 0x30
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#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
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#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
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#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
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#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
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#define MCSMI_EN (1 << 11) // Trap microcontroller range access
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#define BIOS_RLS (1 << 7) // asserts SCI on bit set
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#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
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#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
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#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
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#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
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#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
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#define EOS (1 << 1) // End of SMI (deassert SMI#)
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#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GPE_CNTL 0x42
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#define DEVACT_STS 0x44
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#define SS_CNT 0x50
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#define C3_RES 0x54
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define ALT_GP_SMI_EN2 0x5c
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#define ALT_GP_SMI_STS2 0x5e
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/* Lynxpoint LP */
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#define LP_GPE0_STS_1 0x80 /* GPIO 0-31 */
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#define LP_GPE0_STS_2 0x84 /* GPIO 32-63 */
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#define LP_GPE0_STS_3 0x88 /* GPIO 64-94 */
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#define LP_GPE0_STS_4 0x8c /* Standard GPE */
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#define LP_GPE0_EN_1 0x90
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#define LP_GPE0_EN_2 0x94
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#define LP_GPE0_EN_3 0x98
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#define LP_GPE0_EN_4 0x9c
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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168
src/soc/intel/broadwell/broadwell/pm.h
Normal file
168
src/soc/intel/broadwell/broadwell/pm.h
Normal file
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@ -0,0 +1,168 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_PM_H_
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#define _BROADWELL_PM_H_
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/* ACPI_BASE_ADDRESS / PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_SHIFT 10
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define SMI_EN 0x30
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#define XHCI_SMI_EN (1 << 31)
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#define ME_SMI_EN (1 << 30)
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#define GPIO_UNLOCK_SMI_EN (1 << 27)
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#define INTEL_USB2_EN (1 << 18)
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#define LEGACY_USB2_EN (1 << 17)
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#define PERIODIC_EN (1 << 14)
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#define TCO_EN (1 << 13)
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#define MCSMI_EN (1 << 11)
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#define BIOS_RLS (1 << 7)
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#define SWSMI_TMR_EN (1 << 6)
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#define APMC_EN (1 << 5)
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#define SLP_SMI_EN (1 << 4)
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#define LEGACY_USB_EN (1 << 3)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define UPWRC 0x3c
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#define UPWRC_WS (1 << 8)
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#define UPWRC_WE (1 << 1)
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#define UPWRC_SMI (1 << 0)
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#define GPE_CNTL 0x42
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#define SWGPE_CTRL (1 << 1)
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#define DEVACT_STS 0x44
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#define PM2_CNT 0x50
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#define TCO1_CNT 0x60
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#define TCO_TMR_HLT (1 << 11)
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define GPE0_STS(x) (0x80 + x)
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#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
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#define GPE_63_32 1 /* 0x80/0x90 = GPE[63:32] */
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#define GPE_94_64 2 /* 0x80/0x90 = GPE[94:64] */
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#define GPE_STD 3 /* 0x80/0x90 = Standard GPE */
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#define WADT_STS (1 << 18)
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#define GP27_STS (1 << 16)
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#define PME_B0_STS (1 << 13)
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#define ME_SCI_STS (1 << 12)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN(x) (0x90 + x)
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#define WADT_en (1 << 18)
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#define GP27_EN (1 << 16)
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#define PME_B0_EN (1 << 13)
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#define ME_SCI_EN (1 << 12)
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#define PME_EN (1 << 11)
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#define BATLOW_EN (1 << 10)
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#define PCI_EXP_EN (1 << 9)
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#define TCOSCI_EN (1 << 6)
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#define SWGPE_EN (1 << 2)
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#define HOT_PLUG_EN (1 << 1)
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#define SLEEP_STATE_S0 0
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#define SLEEP_STATE_S3 3
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#define SLEEP_STATE_S5 5
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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uint32_t pm1_cnt;
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uint32_t tco1_sts;
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uint32_t tco2_sts;
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uint32_t gpe0_sts[4];
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uint32_t gpe0_en[4];
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uint16_t gen_pmcon1;
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uint16_t gen_pmcon2;
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uint16_t gen_pmcon3;
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int prev_sleep_state;
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};
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/* PM1_CNT */
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void enable_pm1_control(uint32_t mask);
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void disable_pm1_control(uint32_t mask);
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/* PM1 */
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uint16_t clear_pm1_status(void);
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void enable_pm1(uint16_t events);
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uint32_t clear_smi_status(void);
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/* SMI */
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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/* ALT_GP_SMI */
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uint32_t clear_alt_smi_status(void);
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void enable_alt_smi(uint32_t mask);
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/* TCO */
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uint32_t clear_tco_status(void);
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void enable_tco_sci(void);
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/* GPE0 */
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uint32_t clear_gpe_status(void);
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void clear_gpe_enable(void);
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void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);
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void disable_all_gpe(void);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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/* Return the selected ACPI SCI IRQ */
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int acpi_sci_irq(void);
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#endif
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