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tegra: get rid of struct members that are not used

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First step in cleanup is to at least get rid of junk
we don't need.

BUG=None
TEST=Builds and boots to dev screen
BRANCH=None

Change-Id: I0a31995f0de481e27805cbcec4cdbc905ee00d9e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/176023
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Ronald G. Minnich 2013-11-06 17:37:56 -08:00 • committed by chrome-internal-fetch
commit 032b8a0c9f
3 changed files with 4 additions and 22 deletions
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4
src/soc/nvidia/tegra/displayport.h
View file

@ -171,10 +171,8 @@ enum {
#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10)
struct tegra_dc_dp_data {
struct tegra_dc *dc;
struct tegra_dc_sor_data *sor;
struct tegra_dc_sor_data sor;
void *aux_base;
struct tegra_dc_mode *mode;
struct tegra_dc_dp_link_config link_cfg;
};

19
src/soc/nvidia/tegra124/dp.c
View file

@ -24,7 +24,6 @@
#include <soc/addressmap.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra/dc.h>
/* shit. This is broken. */
#include "sor.h"
#include <soc/nvidia/tegra/displayport.h>
@ -51,13 +50,11 @@ static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
u32 poll_interval_us,
u32 timeout_ms)
{
// unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
u32 reg_val = 0;
printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n",
__func__, reg * 4, timeout_ms);
do {
// udelay(poll_interval_us);
udelay(1);
reg_val = tegra_dpaux_readl(dp, reg);
} while (((reg_val & mask) != exp_val) && (--timeout_ms > 0));
@ -439,9 +436,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
return 0;
}
//struct tegra_dc dc_data = {0};
struct tegra_dc_sor_data sor_data = { 0 };
struct tegra_dc_dp_data dp_data = { 0 };
struct tegra_dc_dp_data dp_data;
static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, u8 * rev)
{
@ -466,20 +461,13 @@ void dp_bringup(u32 winb_addr)
u32 dpcd_rev;
u32 pclk_freq;
// int ret;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
dp->sor = &sor_data;
// dp->sor->dc = dc;
dp->sor->base = (void *)TEGRA_ARM_SOR;
// dp->sor->base_res = base_res;
// dp->sor->sor_clk = clk;
dp->sor->link_cfg = &dp->link_cfg;
dp->sor->portnum = 0;
dp->sor.base = (void *)TEGRA_ARM_SOR;
dp->sor.portnum = 0;
dp->aux_base = (void *)TEGRA_ARM_DPAUX;
/* dp->mode = 0; *//* ???? */
/* read panel info */
if (!tegra_dc_dpcd_read_rev(dp, (u8 *) & dpcd_rev)) {
@ -497,7 +485,6 @@ void dp_bringup(u32 winb_addr)
pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1
printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq);
// void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr)
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
u32 pclkfreq, u32 linkfreq);

3
src/soc/nvidia/tegra124/sor.h
View file

@ -885,11 +885,8 @@ struct tegra_dc_dp_link_config {
* having two channels.
*/
struct tegra_dc_sor_data {
struct tegra_dc *dc;
void *base;
u8 portnum; /* 0 or 1 */
const struct tegra_dc_dp_link_config *link_cfg;
int power_is_up;
};