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tegra124: Fix up the PLLX divider table.

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This PLL feeds the CPUs, and, when using a 12 MHz external oscillator like on
nyan, was running the CPUs at 108 MHz. The new settings bring the frequency in
that case and the other oscillator frequencies up as close as they can be to
1.9 GHz without going over. I went for that frequency because it was in a
comment in the source, but the data sheet suggests that we could actually go
at 2.0 GHz.

The manual doesn't actually say what formula is used when applying the M/N
divider, but it appears to be:

(osc * n) / (m * (2 ^ p)) = output frequency.

It's interesting that the divider type is called M/N but the formula
effectively has N/M in it, but I suppose that works out if you're dividing
by it. Because we're going from a pretty low frequency to a pretty high
frequency, n is generally high and m and p are generally low. m and n are
limitted to 8 bits, so there aren't many combinations that can bring the
frequency up enough.

BUG=None
TEST=Built and booted into depthcharge on nyan. Saw that it ran much faster.
BRANCH=None

Change-Id: I5af9d33a1f9c4420235127a4e8276656fd67b170
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173778
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-10-20 22:57:20 -07:00 • committed by chrome-internal-fetch
commit 3362cf3a7d
1 changed files with 7 additions and 7 deletions
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14
src/soc/nvidia/tegra124/clock.c
View file

@ -46,13 +46,13 @@ struct clk_pll_table tegra_pll_x_table[16] = {
* m 7:0 8
* p 23:20 4
*/
[OSC_FREQ_OSC13]{216,13,1,8},
[OSC_FREQ_OSC19P2]{180,16,1,4},
[OSC_FREQ_OSC12]{216,12,1,8},
[OSC_FREQ_OSC26]{216,26,1,8},
[OSC_FREQ_OSC16P8]{180,14,1,4},
[OSC_FREQ_OSC38P4]{180,16,1,4},
[OSC_FREQ_OSC48]{216,12,1,8},
[OSC_FREQ_OSC13]{146,1,0,8},
[OSC_FREQ_OSC19P2]{98,1,0,4},
[OSC_FREQ_OSC12]{157,1,0,8},
[OSC_FREQ_OSC26]{73,1,0,8},
[OSC_FREQ_OSC16P8]{113,1,0,4},
[OSC_FREQ_OSC38P4]{98,2,0,4},
[OSC_FREQ_OSC48]{157,4,0,8},
};
void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor)