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tegra124: add basic SPI driver

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This adds a basic SPI driver for reading SPI flash content. It uses
the DMA engine, albeit in a sub-optimal manner for now with the
intention of future optimizations to shave a few dozen milliseconds
off boot time.

BUG=none
BRANCH=none
TEST=read SPI flash on Nyan

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ic68348add093f014a6b3f08ace5719de035629be
Reviewed-on: https://chromium-review.googlesource.com/172952
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
David Hendricks 2013-10-08 20:55:13 -07:00 • committed by chrome-internal-fetch
commit 5f861f13c7
7 changed files with 692 additions and 1 deletions
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16
src/mainboard/google/nyan/Kconfig
View file

@ -55,4 +55,20 @@ config BCT_CFG_EMMC
endchoice
config BOOT_MEDIA_SPI_BUS
int "SPI bus with boot media ROM"
range 1 6
depends on BCT_CFG_SPI
default 4
help
Which SPI bus the boot media is connected to.
config BOOT_MEDIA_SPI_CHIP_SELECT
int "Chip select for SPI boot media"
range 0 3
depends on BCT_CFG_SPI
default 0
help
Which chip select to use for boot media.
endif # BOARD_GOOGLE_NYAN

16
src/mainboard/google/nyan/bootblock.c
View file

@ -23,6 +23,7 @@
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/clock.h>
#include <soc/nvidia/tegra124/pinmux.h>
#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
#include "pmic.h"
@ -61,4 +62,19 @@ void bootblock_mainboard_init(void)
i2c_init(4);
pmic_init(4);
/* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX,
PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX,
PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 clock */
pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX,
PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */
pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX,
PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
// spi_init();
tegra_spi_init(4);
}

8
src/soc/nvidia/tegra124/Kconfig
View file

@ -59,6 +59,14 @@ config STACK_SIZE
hex
default 0x800
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x803c0000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00013000
choice CONSOLE_SERIAL_TEGRA124_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UARTA

6
src/soc/nvidia/tegra124/Makefile.inc
View file

@ -4,10 +4,12 @@ bootblock-y += bootblock.c
bootblock-y += bootblock_asm.S
bootblock-y += cbfs.c
bootblock-y += clock.c
bootblock-y += dma.c
bootblock-y += i2c.c
bootblock-y += dma.c
bootblock-y += monotonic_timer.c
bootblock-y += power.c
bootblock-y += spi.c
bootblock-y += ../tegra/gpio.c
bootblock-y += ../tegra/i2c.c
bootblock-y += ../tegra/pingroup.c
@ -18,14 +20,18 @@ bootblock-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
endif
romstage-y += cbfs.c
romstage-y += dma.c
romstage-y += monotonic_timer.c
romstage-y += spi.c
romstage-y += timer.c
ifeq ($(CONFIG_EARLY_CONSOLE),y)
romstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
endif
ramstage-y += cbfs.c
ramstage-y += dma.c
ramstage-y += monotonic_timer.c
ramstage-y += spi.c
ramstage-y += timer.c
ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c

6
src/soc/nvidia/tegra124/cbfs.c
View file

@ -20,7 +20,11 @@
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include "spi.h"
int init_default_cbfs_media(struct cbfs_media *media)
{
return -1;
return initialize_tegra_spi_cbfs_media(media,
(void*)CONFIG_CBFS_CACHE_ADDRESS,
CONFIG_CBFS_CACHE_SIZE);
}

595
src/soc/nvidia/tegra124/spi.c Normal file
View file

@ -0,0 +1,595 @@
/*
* NVIDIA Tegra SPI controller (T114 and later)
*
* Copyright (c) 2010-2013 NVIDIA Corporation
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <assert.h>
#include <cbfs.h>
#include <cbfs_core.h>
#include <inttypes.h>
#include <spi-generic.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>
#include <console/console.h>
#include <soc/addressmap.h>
#include <delay.h>
#include "dma.h"
#include "spi.h"
#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x)
#else
# define DEBUG_SPI(x,...)
#endif
/*
* 64 packets in FIFO mode, BLOCK_SIZE packets in DMA mode. Packets can vary
* in size from 4 to 32 bits. To keep things simple we'll use 8-bit packets.
*/
#define SPI_PACKET_SIZE_BYTES 1
#define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES)
#define SPI_MAX_TRANSFER_BYTES_DMA (65536 * SPI_PACKET_SIZE_BYTES)
/* COMMAND1 */
#define SPI_CMD1_GO (1 << 31)
#define SPI_CMD1_M_S (1 << 30)
#define SPI_CMD1_MODE_MASK 0x3
#define SPI_CMD1_MODE_SHIFT 28
#define SPI_CMD1_CS_SEL_MASK 0x3
#define SPI_CMD1_CS_SEL_SHIFT 26
#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
#define SPI_CMD1_CS_SW_HW (1 << 21)
#define SPI_CMD1_CS_SW_VAL (1 << 20)
#define SPI_CMD1_IDLE_SDA_MASK 0x3
#define SPI_CMD1_IDLE_SDA_SHIFT 18
#define SPI_CMD1_BIDIR (1 << 17)
#define SPI_CMD1_LSBI_FE (1 << 16)
#define SPI_CMD1_LSBY_FE (1 << 15)
#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
#define SPI_CMD1_RX_EN (1 << 12)
#define SPI_CMD1_TX_EN (1 << 11)
#define SPI_CMD1_PACKED (1 << 5)
#define SPI_CMD1_BIT_LEN_MASK 0x1f
#define SPI_CMD1_BIT_LEN_SHIFT 0
/* COMMAND2 */
#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
/* SPI_TRANS_STATUS */
#define SPI_STATUS_RDY (1 << 30)
#define SPI_STATUS_SLV_IDLE_COUNT_MASK 0xff
#define SPI_STATUS_SLV_IDLE_COUNT_SHIFT 16
#define SPI_STATUS_BLOCK_COUNT 0xffff
#define SPI_STATUS_BLOCK_COUNT_SHIFT 0
/* SPI_FIFO_STATUS */
#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31)
#define SPI_FIFO_STATUS_FRAME_END (1 << 30)
#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15)
#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14)
#define SPI_FIFO_STATUS_ERR (1 << 8)
#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7)
#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6)
#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5)
#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4)
#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3)
#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2)
#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1)
#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0)
/* SPI_DMA_CTL */
#define SPI_DMA_CTL_DMA (1 << 31)
#define SPI_DMA_CTL_CONT (1 << 30)
#define SPI_DMA_CTL_IE_RX (1 << 29)
#define SPI_DMA_CTL_IE_TX (1 << 28)
#define SPI_DMA_CTL_RX_TRIG_MASK 0x3
#define SPI_DMA_CTL_RX_TRIG_SHIFT 19
#define SPI_DMA_CTL_TX_TRIG_MASK 0x3
#define SPI_DMA_CTL_TX_TRIG_SHIFT 15
/* SPI_DMA_BLK */
#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xff
#define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0
struct tegra_spi_regs {
u32 command1; /* 0x000: SPI_COMMAND1 */
u32 command2; /* 0x004: SPI_COMMAND2 */
u32 timing1; /* 0x008: SPI_CS_TIM1 */
u32 timing2; /* 0x00c: SPI_CS_TIM2 */
u32 trans_status; /* 0x010: SPI_TRANS_STATUS */
u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */
u32 tx_data; /* 0x018: SPI_TX_DATA */
u32 rx_data; /* 0x01c: SPI_RX_DATA */
u32 dma_ctl; /* 0x020: SPI_DMA_CTL */
u32 dma_blk; /* 0x024: SPI_DMA_BLK */
u8 rsvd[0xe0]; /* 0x028-0x107: reserved */
u32 tx_fifo; /* 0x108: SPI_FIFO1 */
u8 rsvd2[0x7c]; /* 0x10c-0x187 reserved */
u32 rx_fifo; /* 0x188: SPI_FIFO2 */
u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
} __attribute__((packed));
struct tegra_spi_channel tegra_spi_channels[TEGRA124_NUM_SPI_CHANNELS] = {
/*
* Note: Tegra pinmux must be setup for corresponding SPI channel in
* order for its registers to be accessible. If pinmux has not been
* set up, access to the channel's registers will simply hang.
*
* TODO(dhendrix): Clarify or remove this comment (is clock setup
* necessary first, or just pinmux, or both?)
*/
{
.slave = { .bus = 1, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE,
},
{
.slave = { .bus = 2, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE,
},
{
.slave = { .bus = 3, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE,
},
{
.slave = { .bus = 4, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE,
},
{
.slave = { .bus = 5, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE,
},
{
.slave = { .bus = 6, },
.regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE,
},
};
void spi_init(void)
{
}
void tegra_spi_init(unsigned int bus)
{
int i;
for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) {
struct tegra_spi_regs *regs;
if (tegra_spi_channels[i].slave.bus == bus)
regs = tegra_spi_channels[i].regs;
else
continue;
/* software drives chip-select, set value to high */
setbits_le32(&regs->command1,
SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL);
/* 8-bit transfers, unpacked mode, most significant bit first */
clrbits_le32(&regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED);
setbits_le32(&regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
/* flush FIFOs */
setbits_le32(&regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH |
SPI_FIFO_STATUS_TX_FIFO_FLUSH);
while (read32(&regs->fifo_status) &
(SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH))
;
}
printk(BIOS_INFO, "Tegra SPI bus %d initialized.\n", bus);
}
static struct tegra_spi_channel * const to_tegra_spi(int bus) {
int i;
struct tegra_spi_channel *channel = NULL;
for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) {
if (tegra_spi_channels[i].slave.bus == bus)
channel = &tegra_spi_channels[i];
}
return channel;
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
if (cs < 0 || cs > 3)
return 0;
if (!to_tegra_spi(bus))
return 0;
return 1;
}
void spi_cs_activate(struct spi_slave *slave)
{
struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs;
u32 val;
val = read32(&regs->command1);
/* select appropriate chip-select line */
val &= ~(SPI_CMD1_CS_SEL_MASK << SPI_CMD1_CS_SEL_SHIFT);
val |= (slave->cs << SPI_CMD1_CS_SEL_SHIFT);
/* drive chip-select with the inverse of the "inactive" value */
if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs))
val &= ~SPI_CMD1_CS_SW_VAL;
else
val |= SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs;
u32 val;
val = read32(&regs->command1);
if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs))
val |= SPI_CMD1_CS_SW_VAL;
else
val &= ~SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
}
static void print_fifo_status(struct tegra_spi_channel *spi)
{
u32 status = read32(&spi->regs->fifo_status);
printk(BIOS_DEBUG, "Raw FIFO status: 0x%08x\n", status);
if (status & SPI_FIFO_STATUS_TX_FIFO_OVF)
printk(BIOS_DEBUG, "\tTx overflow detected\n");
if (status & SPI_FIFO_STATUS_TX_FIFO_UNR)
printk(BIOS_DEBUG, "\tTx underrun detected\n");
if (status & SPI_FIFO_STATUS_RX_FIFO_OVF)
printk(BIOS_DEBUG, "\tRx overflow detected\n");
if (status & SPI_FIFO_STATUS_RX_FIFO_UNR)
printk(BIOS_DEBUG, "\tRx underrun detected\n");
printk(BIOS_DEBUG, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n",
read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data));
printk(BIOS_DEBUG, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n",
read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data));
}
static void clear_fifo_status(struct tegra_spi_channel *spi)
{
clrbits_le32(&spi->regs->fifo_status,
(SPI_FIFO_STATUS_ERR |
SPI_FIFO_STATUS_TX_FIFO_OVF |
SPI_FIFO_STATUS_TX_FIFO_UNR |
SPI_FIFO_STATUS_RX_FIFO_OVF |
SPI_FIFO_STATUS_RX_FIFO_UNR) << 4);
}
static void dump_regs(struct tegra_spi_channel *spi,
struct apb_dma_channel *dma)
{
printk(BIOS_DEBUG, "DMA regs:\n");
printk(BIOS_DEBUG, "\tahb_ptr: 0x%08x\n"
"\tapb_ptr: 0x%08x\n"
"\tahb_seq: 0x%08x\n"
"\tapb_seq: 0x%08x\n"
"\tcsr: 0x%08x\n"
"\tcsre: 0x%08x\n"
"\twcount: 0x%08x\n"
"\tdma_byte_sta: 0x%08x\n"
"\tword_transfer: 0x%08x\n",
read32(&dma->regs->ahb_ptr),
read32(&dma->regs->apb_ptr),
read32(&dma->regs->ahb_seq),
read32(&dma->regs->apb_seq),
read32(&dma->regs->csr),
read32(&dma->regs->csre),
read32(&dma->regs->wcount),
read32(&dma->regs->dma_byte_sta),
read32(&dma->regs->word_transfer));
printk(BIOS_DEBUG, "SPI regs:\n");
printk(BIOS_DEBUG, "\tdma_blk: 0x%08x\n"
"\tcommand1: 0x%08x\n"
"\tdma_ctl: 0x%08x\n"
"\ttrans_status: 0x%08x\n",
read32(&spi->regs->dma_blk),
read32(&spi->regs->command1),
read32(&spi->regs->dma_ctl),
read32(&spi->regs->trans_status));
}
int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
void *din, unsigned int bitsin)
{
unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8;
int ret = 0;
struct apb_dma_channel *dma;
struct tegra_spi_channel *spi = to_tegra_spi(slave->bus);
ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0);
/* tegra bus numbers start at 1 */
ASSERT(slave->bus >= 1 && slave->bus <= TEGRA124_NUM_SPI_CHANNELS);
dma = dma_claim();
if (!dma) {
printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__);
return -1;
}
/* flush FIFOs */
setbits_le32(&spi->regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH |
SPI_FIFO_STATUS_TX_FIFO_FLUSH);
while (read32(&spi->regs->fifo_status) & (SPI_FIFO_STATUS_RX_FIFO_FLUSH |
SPI_FIFO_STATUS_TX_FIFO_FLUSH))
;
/* A few common parameters used for both transmit and receive */
/* APB bus width = 8-bits, address wrap for each word */
clrbits_le32(&dma->regs->apb_seq, 0x7 << 28);
/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
* no address wrapping */
clrsetbits_le32(&dma->regs->ahb_seq,
(0x7 << 24) | (0x7 << 16), 0x4 << 24);
/* Set ONCE mode to transfer one "blocK" at a time (64KB). */
setbits_le32(&dma->regs->csr, 1 << 27);
/*
* Notes for transmit and receive, experimentally determined (need to
* verify):
* - WCOUNT seems to be an "n-1" count, but the documentation does not
* make this clear. Without the -1 dma_byte_sta will show 1 AHB word
* (4 bytes) higher than it should and Tx overrun / Rx underrun will
* likely occur.
*
* - dma_byte_sta is always a multiple 4, so we check for
* dma_byte_sta < length
*
* - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually
* (set bit to clear) between each transaction. Otherwise the next
* transaction does not start.
*/
if (out_bytes && dout) {
printk(BIOS_SPEW, "%s: Writing %d bytes\n",
__func__, out_bytes);
/* set AHB & APB address pointers */
write32((u32)dout, &dma->regs->ahb_ptr);
write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr);
setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
/* FIXME: calculate word count so that it corresponds to bus width */
write32(out_bytes - 1, &dma->regs->wcount);
/* specify BLOCK_SIZE in SPI_DMA_BLK */
write32(out_bytes - 1, &spi->regs->dma_blk);
/* Set DMA direction for AHB (DRAM) --> APB (SPI) */
setbits_le32(&dma->regs->csr, (1 << 28));
/* write to SPI_TRANS_STATUS RDY bit to clear it */
setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
dma_start(dma);
/* set DMA bit in SPI_DMA_CTL to start */
setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
/* FIXME: delay loops should be "thread" friendly */
while ((read32(&dma->regs->dma_byte_sta) < out_bytes) ||
dma_busy(dma))
;
dma_stop(dma);
while ((read32(&spi->regs->trans_status) &
SPI_STATUS_BLOCK_COUNT) != out_bytes)
;
clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
}
if (in_bytes && din) {
printk(BIOS_SPEW, "%s: Reading %d bytes\n",
__func__, in_bytes);
/* set AHB & APB address pointers */
write32((u32)din, &dma->regs->ahb_ptr);
write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr);
setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
write32(in_bytes - 1, &dma->regs->wcount);
/* specify BLOCK_SIZE in SPI_DMA_BLK */
write32(in_bytes - 1, &spi->regs->dma_blk);
/* Set DMA direction for APB (SPI) --> AHB (DRAM) */
clrbits_le32(&dma->regs->csr, 1 << 28);
/* write to SPI_TRANS_STATUS RDY bit to clear it */
setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
/* set DMA bit in SPI_DMA_CTL to start */
setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
/* start APBDMA after SPI DMA so we don't read empty bytes from Rx FIFO */
dma_start(dma);
/* FIXME: delay loops should be "thread" friendly */
while ((read32(&spi->regs->trans_status) &
SPI_STATUS_BLOCK_COUNT) != in_bytes)
;
clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
while ((read32(&dma->regs->dma_byte_sta) < in_bytes) ||
dma_busy(dma))
;
dma_stop(dma);
}
dma_release(dma);
/*
* FIXME: 4-byte unaligned transfers will cause FIFO overrun/underruns.
* The DMA controller will attempt to send/receive more bytes than it
* should, but the SPI controller is smart enough not to attempt to
* transmit more bytes than BLOCK_SIZE in the SPI_DMA_BLK register.
*/
if (din && (in_bytes % 4)) {
if (read32(&spi->regs->fifo_status) &
SPI_FIFO_STATUS_RX_FIFO_UNR) {
printk(BIOS_DEBUG, "SPI: Ignoring Rx FIFO underrun.\n");
setbits_le32(&spi->regs->fifo_status,
SPI_FIFO_STATUS_RX_FIFO_UNR);
}
}
if (dout && (out_bytes % 4)) {
if (read32(&spi->regs->fifo_status) &
SPI_FIFO_STATUS_TX_FIFO_OVF) {
printk(BIOS_DEBUG, "SPI: Ignoring Tx FIFO overrun.\n");
setbits_le32(&spi->regs->fifo_status,
SPI_FIFO_STATUS_TX_FIFO_OVF);
}
}
if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR) {
ret = -1;
dump_regs(spi, dma);
print_fifo_status(spi);
clear_fifo_status(spi);
}
return ret;
}
/* SPI as CBFS media. */
struct tegra_spi_media {
struct spi_slave *slave;
struct cbfs_simple_buffer buffer;
};
static int tegra_spi_cbfs_open(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_open\n");
return 0;
}
static int tegra_spi_cbfs_close(struct cbfs_media *media)
{
DEBUG_SPI("tegra_spi_cbfs_close\n");
return 0;
}
#define JEDEC_READ 0x03
#define JEDEC_READ_OUTSIZE 0x04
/* JEDEC_READ_INSIZE : any length */
static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
size_t offset, size_t count)
{
struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context;
u8 spi_read_cmd[JEDEC_READ_OUTSIZE];
int ret = count;
/* TODO: Dual mode (BOTH_EN_BIT) and packed mode */
spi_read_cmd[0] = JEDEC_READ;
spi_read_cmd[1] = (offset >> 16) & 0xff;
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
/* assert /CS */
spi_cs_activate(spi->slave);
if (spi_xfer(spi->slave, spi_read_cmd,
sizeof(spi_read_cmd) * 8, NULL, 0) < 0)
goto tegra_spi_cbfs_read_exit;
while (count > 0) {
unsigned int remaining;
/* FIXME: shouldn't need to subtract 4 here... */
remaining = MIN(count, SPI_MAX_TRANSFER_BYTES_DMA - 4);
count -= remaining;
if (spi_xfer(spi->slave, NULL, 0, dest, remaining * 8)) {
ret = -1;
printk(BIOS_ERR, "SPI failed to transfer %u bytes\n",
remaining);
break;
}
}
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
spi_cs_deactivate(spi->slave);
return (ret < 0) ? 0 : ret;
}
static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset,
size_t count)
{
struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
void *map;
DEBUG_SPI("tegra_spi_cbfs_map\n");
map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count);
printk(BIOS_INFO, "%s: map: 0x%p\n", __func__, map);
return map;
}
static void *tegra_spi_cbfs_unmap(struct cbfs_media *media,
const void *address)
{
struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context;
DEBUG_SPI("tegra_spi_cbfs_unmap\n");
return cbfs_simple_buffer_unmap(&spi->buffer, address);
}
int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
void *buffer_address,
size_t buffer_size)
{
// TODO Replace static variable to support multiple streams.
static struct tegra_spi_media context;
static struct tegra_spi_channel *channel;
channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
DEBUG_SPI("Initializing CBFS media on SPI\n");
context.slave = &channel->slave;
context.buffer.allocated = context.buffer.last_allocate = 0;
context.buffer.buffer = buffer_address;
context.buffer.size = buffer_size;
media->context = (void*)&context;
media->open = tegra_spi_cbfs_open;
media->close = tegra_spi_cbfs_close;
media->read = tegra_spi_cbfs_read;
media->map = tegra_spi_cbfs_map;
media->unmap = tegra_spi_cbfs_unmap;
return 0;
}

46
src/soc/nvidia/tegra124/spi.h Normal file
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@ -0,0 +1,46 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __NVIDIA_TEGRA124_SPI_H__
#define __NVIDIA_TEGRA124_SPI_H__
#include <stddef.h>
#include <spi-generic.h>
struct tegra_spi_channel {
struct spi_slave slave;
struct tegra_spi_regs *regs;
/*
* max transfer size and dma_buf address will be set by
* mainboard-specific code, depending on the requirements for
* the device connected
*/
unsigned int max_transfer_size;
void *dma_buf;
};
#define TEGRA124_NUM_SPI_CHANNELS 6
extern struct tegra_spi_channel tegra_spi_channels[];
struct cbfs_media;
int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
void *buffer_address,
size_t buffer_size);
void tegra_spi_init(unsigned int bus);
#endif /* __NVIDIA_TEGRA124_SPI_H__ */