broadwell: pch.h: split SerialIO into new header
Move the SerialIO related register/bit defines into a separate header file at broadwell/serialio.h BUG=chrome-os-partner:28234 TEST=None Change-Id: I84fea5fd0b2c82f37e7aa025ed0188e0bf19c411 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198551 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
099af14676
commit
4f3c028686
2 changed files with 94 additions and 66 deletions
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@ -274,72 +274,6 @@ void pch_enable_lpc(void);
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#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
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#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
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/* Serial IO IOBP Registers */
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#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
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#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
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#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
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#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
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#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
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#define SIO_IOBP_GPIODF 0xcb000154
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#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
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#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
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#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
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#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
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#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
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#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
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#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
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#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
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#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
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#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
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#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
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#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
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#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
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/* PORTCTRL 2-8 have the same layout */
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#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
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#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
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#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
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#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
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#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
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#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
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#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
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#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
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#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
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#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
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#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
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#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
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#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
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#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
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/* Serial IO Devices */
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#define SIO_ID_SDMA 0 /* D21:F0 */
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#define SIO_ID_I2C0 1 /* D21:F1 */
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#define SIO_ID_I2C1 2 /* D21:F2 */
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#define SIO_ID_SPI0 3 /* D21:F3 */
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#define SIO_ID_SPI1 4 /* D21:F4 */
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#define SIO_ID_UART0 5 /* D21:F5 */
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#define SIO_ID_UART1 6 /* D21:F6 */
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#define SIO_ID_SDIO 7 /* D23:F0 */
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#define SIO_REG_PPR_CLOCK 0x800
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#define SIO_REG_PPR_CLOCK_EN (1 << 0)
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#define SIO_REG_PPR_RST 0x804
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#define SIO_REG_PPR_RST_ASSERT 0x3
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#define SIO_REG_PPR_GEN 0x808
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#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
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#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
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#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
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#define SIO_REG_AUTO_LTR 0x814
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#define SIO_REG_SDIO_PPR_GEN 0x1008
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#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
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#define SIO_REG_SDIO_PPR_CMD12 0x3c
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#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
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#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
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#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
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#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
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#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
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/* PCI Configuration Space (D31:F3): SMBus */
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#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
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#define SMB_BASE 0x20
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94
src/soc/intel/broadwell/broadwell/serialio.h
Normal file
94
src/soc/intel/broadwell/broadwell/serialio.h
Normal file
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@ -0,0 +1,94 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_SERIALIO_H_
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#define _BROADWELL_SERIALIO_H_
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/* Serial IO IOBP Registers */
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#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
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#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
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#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
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#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
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#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
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#define SIO_IOBP_GPIODF 0xcb000154
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#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
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#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
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#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
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#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
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#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
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#define SIO_IOBP_GPIODF_UART0_BYTE_ACCESS (1 << 10)
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#define SIO_IOBP_GPIODF_UART1_BYTE_ACCESS (1 << 11)
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#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
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#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
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#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
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#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
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#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
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#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
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#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
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#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
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/* PORTCTRL 2-8 have the same layout */
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#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
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#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
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#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
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#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
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#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
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#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
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#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
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#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
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#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
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#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
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#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
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#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
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#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
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#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
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/* Serial IO Devices */
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#define SIO_ID_SDMA 0 /* D21:F0 */
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#define SIO_ID_I2C0 1 /* D21:F1 */
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#define SIO_ID_I2C1 2 /* D21:F2 */
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#define SIO_ID_SPI0 3 /* D21:F3 */
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#define SIO_ID_SPI1 4 /* D21:F4 */
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#define SIO_ID_UART0 5 /* D21:F5 */
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#define SIO_ID_UART1 6 /* D21:F6 */
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#define SIO_ID_SDIO 7 /* D23:F0 */
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#define SIO_REG_PPR_CLOCK 0x800
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#define SIO_REG_PPR_CLOCK_EN (1 << 0)
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#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
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#define SIO_REG_PPR_CLOCK_M_DIV 0x25a
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#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff
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#define SIO_REG_PPR_RST 0x804
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#define SIO_REG_PPR_RST_ASSERT 0x3
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#define SIO_REG_PPR_GEN 0x808
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#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
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#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
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#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
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#define SIO_REG_AUTO_LTR 0x814
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#define SIO_REG_SDIO_PPR_GEN 0x1008
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#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
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#define SIO_REG_SDIO_PPR_CMD12 0x3c
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#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
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#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
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#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
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#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
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#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
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#endif
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