broadwell: ACPI: Clean up use of base address defines
Use the newly provided broadwell/iomap.h to get the base addresses that need to be defined in ACPI. Add device resource consumption ResourceTemplate() for these base addresses. BUG=chrome-os-partner:28234 TEST=None Change-Id: I8dffd7e7d0722868c5477bc4b2b9d4621406a223 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198912 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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3 changed files with 28 additions and 4 deletions
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@ -178,7 +178,7 @@ Device (LPCB)
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IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
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IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
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IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
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0x1, 0xff)
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})
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@ -19,6 +19,7 @@
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*/
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/* Intel Cougar Point PCH support */
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#include <soc/intel/broadwell/broadwell/iomap.h>
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Scope(\)
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{
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@ -31,9 +32,9 @@ Scope(\)
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TRP0, 8 // IO-Trap at 0x808
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}
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// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
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OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field(RCRB, DWordAcc, Lock, Preserve)
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// Root Complex Register Block
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OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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Field (RCRB, DWordAcc, Lock, Preserve)
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{
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Offset(0x0000), // Backbone
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Offset(0x1000), // Chipset
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@ -18,6 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <soc/intel/broadwell/broadwell/iomap.h>
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Name(_HID,EISAID("PNP0A08")) // PCIe
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Name(_CID,EISAID("PNP0A03")) // PCI
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@ -243,6 +244,28 @@ Method (_CRS, 0, Serialized)
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/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
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#include "acpi/haswell_pci_irqs.asl"
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/* PCI Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_UID, 1)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
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Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
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Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
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Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
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Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
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})
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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Return (PDRS)
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}
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}
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/* Configurable TDP */
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