broadwell: ACPI: Clean up use of base address defines

Use the newly provided broadwell/iomap.h to get the base addresses
that need to be defined in ACPI.

Add device resource consumption ResourceTemplate() for these
base addresses.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I8dffd7e7d0722868c5477bc4b2b9d4621406a223
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 09:30:19 -07:00 committed by chrome-internal-fetch
commit 34e4788955
3 changed files with 28 additions and 4 deletions

View file

@ -178,7 +178,7 @@ Device (LPCB)
IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
0x1, 0xff)
})

View file

@ -19,6 +19,7 @@
*/
/* Intel Cougar Point PCH support */
#include <soc/intel/broadwell/broadwell/iomap.h>
Scope(\)
{
@ -31,9 +32,9 @@ Scope(\)
TRP0, 8 // IO-Trap at 0x808
}
// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
// Root Complex Register Block
OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
Field (RCRB, DWordAcc, Lock, Preserve)
{
Offset(0x0000), // Backbone
Offset(0x1000), // Chipset

View file

@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/intel/broadwell/broadwell/iomap.h>
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
@ -243,6 +244,28 @@ Method (_CRS, 0, Serialized)
/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
#include "acpi/haswell_pci_irqs.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return (PDRS)
}
}
/* Configurable TDP */