broadwell: Clean up SATA ramstage driver
- Remove the IDE and SATA (plan) options since they are not supported by the chipset. - Remove the LynxPoint-LP specific checks since only LP variant is supported. - Add code to static power gate the unused ports. BUG=chrome-os-partner:28234 TEST=None Change-Id: Ic161abb167cc406163b12c643685a6958382c4a9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199367 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
0ef5961ebe
commit
ffa5743f74
1 changed files with 108 additions and 203 deletions
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@ -24,10 +24,11 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <delay.h>
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#include "pch.h"
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typedef struct southbridge_intel_lynxpoint_config config_t;
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#include <broadwell/iobp.h>
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#include <broadwell/ramstage.h>
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#include <broadwell/rcba.h>
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#include <broadwell/sata.h>
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#include <chip.h>
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static inline u32 sir_read(struct device *dev, int idx)
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{
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@ -43,191 +44,105 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u32 reg32, abar;
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u16 reg16;
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printk(BIOS_DEBUG, "SATA: Initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
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return;
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}
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/* SATA configuration */
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printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, 0x0007);
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if (config->ide_legacy_combined) {
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printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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pci_write_config8(dev, 0x09, 0x80);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
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/* for AHCI, Port Enable is managed in memory mapped space */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= 0x8000 | config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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udelay(2);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Setup register 98h */
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reg32 = pci_read_config16(dev, 0x98);
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reg32 |= 1 << 19; /* BWG step 6 */
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reg32 |= 1 << 22; /* BWG step 5 */
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reg32 &= ~(0x3f << 7);
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reg32 |= 0x04 << 7; /* BWG step 7 */
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reg32 |= 1 << 20; /* BWG step 8 */
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reg32 &= ~(0x03 << 5);
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reg32 |= 1 << 5; /* BWG step 9 */
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reg32 |= 1 << 18; /* BWG step 10 */
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reg32 |= 1 << 29; /* BWG step 11 */
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
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pci_write_config32(dev, 0x98, reg32);
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/* Port enable */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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/* Setup register 9Ch */
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reg16 = 0; /* Disable alternate ID */
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reg16 = 1 << 5; /* BWG step 12 */
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pci_write_config16(dev, 0x9c, reg16);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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} else if(config->sata_ahci) {
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u32 abar;
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/* SATA Initialization register */
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reg32 = 0x183;
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reg32 |= (config->sata_port_map ^ 0x3f) << 24;
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reg32 |= (config->sata_devslp_mux & 1) << 15;
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pci_write_config32(dev, 0x94, reg32);
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printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
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reg32 &= ~0x00020060; // clear SXS+EMS+PMS
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reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
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write32(abar + 0x00, reg32);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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/* PI (Ports implemented) */
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write32(abar + 0x0c, config->sata_port_map);
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = read32(abar + 0x24);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/*
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* Static Power Gating for unused ports
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*/
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reg32 = RCBA32(0x3a84);
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/* Port 3 and 2 disabled */
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if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0)
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reg32 |= (1 << 24) | (1 << 26);
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/* Port 1 and 0 disabled */
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if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0)
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reg32 |= (1 << 20) | (1 << 18);
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RCBA32(0x3a84) = reg32;
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/* for AHCI, Port Enable is managed in memory mapped space */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= 0x8000 | config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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udelay(2);
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/* Setup register 98h */
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reg32 = pci_read_config16(dev, 0x98);
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reg32 |= 1 << 19; /* BWG step 6 */
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reg32 |= 1 << 22; /* BWG step 5 */
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reg32 &= ~(0x3f << 7);
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reg32 |= 0x04 << 7; /* BWG step 7 */
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reg32 |= 1 << 20; /* BWG step 8 */
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reg32 &= ~(0x03 << 5);
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reg32 |= 1 << 5; /* BWG step 9 */
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reg32 |= 1 << 18; /* BWG step 10 */
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reg32 |= 1 << 29; /* BWG step 11 */
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if (pch_is_lp()) {
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
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}
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pci_write_config32(dev, 0x98, reg32);
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/* Setup register 9Ch */
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reg16 = 0; /* Disable alternate ID */
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reg16 = 1 << 5; /* BWG step 12 */
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pci_write_config16(dev, 0x9c, reg16);
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/* SATA Initialization register */
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reg32 = 0x183;
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reg32 |= (config->sata_port_map ^ 0x3f) << 24;
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reg32 |= (config->sata_devslp_mux & 1) << 15;
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pci_write_config32(dev, 0x94, reg32);
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
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reg32 &= ~0x00020060; // clear SXS+EMS+PMS
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if (pch_is_lp())
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reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
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write32(abar + 0x00, reg32);
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/* PI (Ports implemented) */
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write32(abar + 0x0c, config->sata_port_map);
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = read32(abar + 0x24);
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/* Enable DEVSLP */
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if (pch_is_lp()) {
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if (config->sata_devslp_disable)
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reg32 &= ~(1 << 3);
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else
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reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
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} else {
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reg32 &= ~0x00000002;
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}
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write32(abar + 0x24, reg32);
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} else {
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printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* Native mode capable on both primary and secondary (0xa)
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* or'ed with enabled (0x50) = 0xf
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*/
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pci_write_config8(dev, 0x09, 0x8f);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0xff);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_SITRE | IDE_ISP_3_CLOCKS |
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IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Port enable */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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}
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/* Enable DEVSLP */
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if (config->sata_devslp_disable)
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reg32 &= ~(1 << 3);
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else
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reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
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write32(abar + 0x24, reg32);
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/* Set Gen3 Transmitter settings if needed */
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if (config->sata_port0_gen3_tx)
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@ -263,14 +178,12 @@ static void sata_init(struct device *dev)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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/* Additional Programming Requirements */
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/* Power Optimizer */
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/*
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* Additional Programming Requirements for Power Optimizer
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*/
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/* Step 1 */
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if (pch_is_lp())
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sir_write(dev, 0x64, 0x883c9003);
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else
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sir_write(dev, 0x64, 0x883c9001);
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sir_write(dev, 0x64, 0x883c9003);
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/* Step 2: SIR 68h[15:0] = 880Ah */
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reg32 = sir_read(dev, 0x68);
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@ -295,10 +208,8 @@ static void sata_init(struct device *dev)
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/* Clock Gating */
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sir_write(dev, 0x70, 0x3f00bf1f);
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if (pch_is_lp()) {
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sir_write(dev, 0x54, 0xcf000f0f);
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sir_write(dev, 0x58, 0x00190000);
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}
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sir_write(dev, 0x54, 0xcf000f0f);
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sir_write(dev, 0x58, 0x00190000);
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reg32 = pci_read_config32(dev, 0x300);
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reg32 |= (1 << 17) | (1 << 16);
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@ -306,21 +217,15 @@ static void sata_init(struct device *dev)
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pci_write_config32(dev, 0x300, reg32);
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}
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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static void sata_enable(device_t dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u16 map = 0;
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if (!config)
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return;
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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if (config->sata_ahci)
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map = 0x0060;
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u16 map = 0x0060;
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map |= (config->sata_port_map ^ 0x3f) << 8;
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