nyan: Clock setup.
I cleaned up the clk_rst struct: no need to have an array for the source select because each thing is an individual entity. There is a bit of a trick in here. I'm using macros to index arrays in the clk_rst struct. Simple reason: if people use the constants we get compile-time checking for simple errors. init_pllx is fixed. The vendor table in u-boot was wrong. BUG=None TEST=builds. Amazing. Prints. Amazing. BRANCH=None Change-Id: I4429b3e5c14c200db6b4dd129eff14261fe1f326 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172106 Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Ronald G. Minnich
chrome-internal-fetch
parent
7dba0dfd25
commit
3697b6454c
6 changed files with 893 additions and 27 deletions
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@ -18,38 +18,19 @@
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*/
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#include <arch/hlt.h>
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#include <arch/io.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <delay.h>
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#include "clock.h"
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#include "pinmux.h"
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static void hacky_hardcoded_uart_setup_function(void)
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{
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// Assert UART reset and enable clock.
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setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6);
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// Enable the clock.
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setbits_le32((void *)(0x60006000 + 4 * 4 + 0), 1 << 6);
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// Set the clock source.
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clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30);
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udelay(2);
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// De-assert reset to UART.
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clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6);
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}
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void main(void)
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{
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void *entry;
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set_avp_clock_to_clkm();
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hacky_hardcoded_uart_setup_function();
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init_clocks();
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// Serial out, tristate off.
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pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
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@ -60,7 +60,7 @@ enum {
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};
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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struct clk_rst_ctlr {
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struct __attribute__ ((__packed__)) clk_rst_ctlr {
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u32 crc_rst_src; /* _RST_SOURCE_0,0x00 */
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u32 crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
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u32 crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
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@ -90,8 +90,63 @@ struct clk_rst_ctlr {
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u32 crc_reserved10; /* _reserved_10, 0xF8 */
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u32 crc_reserved11; /* _reserved_11, 0xFC */
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u32 crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
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/* 0x100 0x1fc */
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u32 src_i2s1;
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u32 src_i2s2;
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u32 src_spdif_out;
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u32 src_spdif_in;
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u32 src_pwm;
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u32 _pad1;
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u32 src_sbc2;
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u32 src_sbc3;
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u32 _pad2[2];
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u32 src_i2c1;
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u32 src_i2c5;
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u32 _pad[1];
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u32 src_sbc1;
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u32 src_disp1;
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u32 src_disp2;
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u32 _pad4[2];
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u32 src_vi;
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u32 _pad5;
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u32 src_sdmmc1;
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u32 src_sdmmc2;
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u32 src_g3d;
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u32 src_g2d;
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u32 src_ndflash;
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u32 src_sdmmc4 ;
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u32 src_vfir;
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u32 src_epp;
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u32 src_mpe;
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u32 src_hsi;
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u32 src_uarta;
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u32 src_uartb;
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u32 src_host1x;
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u32 _pad6[2];
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u32 src_hdmi;
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u32 _pad7[2];
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u32 src_i2c2;
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u32 src_emc0; /* not correctly documented as to address. */
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u32 src_uartc;
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u32 _pad71;
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u32 src_vi_sensor;
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u32 _pad8[2];
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u32 src_sbc4;
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u32 src_i2c3;
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u32 src_sdmmc3;
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u32 src_uartd;
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u32 src_uarte;
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u32 src_vde;
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u32 src_owr;
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u32 src_nor;
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u32 src_csite;
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u32 src_i2s0;
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u32 src_dtv;
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u32 pad9[4];
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u32 src_msenc;
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u32 src_tsec;
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u32 pad10;
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u32 src_osc;
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u32 crc_reserved20[32]; /* _reserved_20, 0x200-27c */
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@ -13,15 +13,162 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <arch/io.h>
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#include <soc/addressmap.h>
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#include "clk_rst.h"
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#include "clock.h"
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#include "flow.h"
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#include "pmc.h"
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE;
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static struct pmc_ctlr *pmc = (void*)TEGRA_PMC_BASE;
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/* only needed in this one place. Avoid namespace pollution. Be green .*/
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struct clk_pll_table {
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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/*
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* Timing tables
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*/
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struct clk_pll_table tegra_pll_x_table[16] = {
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/* T124: 1.9 GHz */
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/*
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* Field Bits Width
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* n 15:8 8
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* m 7:0 8
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* p 23:20 4
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*/
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[OSC_FREQ_OSC13]{216,13,1,8},
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[OSC_FREQ_OSC19P2]{180,16,1,4},
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[OSC_FREQ_OSC12]{216,12,1,8},
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[OSC_FREQ_OSC26]{216,26,1,8},
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[OSC_FREQ_OSC16P8]{180,14,1,4},
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[OSC_FREQ_OSC38P4]{180,16,1,4},
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[OSC_FREQ_OSC48]{216,12,1,8},
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};
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/* one of the very few funcs we might move to common code. */
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static void clock_ll_set_source_divisor(u32 *reg,
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unsigned source, unsigned divisor)
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{
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u32 value;
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value = readl(reg);
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value &= ~OUT_CLK_SOURCE_MASK;
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value |= source << OUT_CLK_SOURCE_SHIFT;
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value &= ~OUT_CLK_DIVISOR_MASK;
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value |= divisor << OUT_CLK_DIVISOR_SHIFT;
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writel(value, reg);
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}
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/* Get the oscillator frequency, from the corresponding hardware
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* configuration field. This is actually a per-soc thing. Avoid the
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* temptation to make it common.
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*/
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static int clock_get_osc_freq(void)
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{
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u32 reg;
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reg = readl(&clk_rst->crc_osc_ctrl);
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reg >>= OSC_CTRL_OSC_FREQ_SHIFT;
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return reg;
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}
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static void adjust_pllp_out_freqs(void)
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{
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u32 reg;
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struct clk_pll *pll = &clk_rst->crc_pll[2/*CLOCK_ID_PERIPH*/];
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/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
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reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
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reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
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| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
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writel(reg, &pll->pll_out[0]);
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reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
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reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
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| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
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writel(reg, &pll->pll_out[1]);
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}
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static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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u32 reg;
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/* If PLLX is already enabled, just return */
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
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return 0;
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}
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/* Disable IDDQ */
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reg = readl(&clk_rst->crc_pllx_misc3);
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reg &= ~PLLX_IDDQ_MASK;
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writel(reg, &clk_rst->crc_pllx_misc3);
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udelay(2);
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
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reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
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writel(reg, &pll->pll_base);
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/* Set cpcon to PLLX_MISC */
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reg = (cpcon << PLL_CPCON_SHIFT);
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/* Set dccon to PLLX_MISC if freq > 600MHz - still needed for T124? */
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if (divn > 600)
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reg |= (1 << PLL_DCCON_SHIFT);
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writel(reg, &pll->pll_misc);
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/* Disable BYPASS */
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reg = readl(&pll->pll_base);
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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/* Set lock_enable to PLLX_MISC */
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reg = readl(&pll->pll_misc);
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reg |= PLL_LOCK_ENABLE_MASK;
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writel(reg, &pll->pll_misc);
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/* Enable PLLX last, as per JZ */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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return 0;
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}
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void init_pllx(void)
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{
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int osc;
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struct clk_pll_table *sel;
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struct clk_pll_simple *pll = &clk_rst->crc_pll_simple[0/*SIMPLE_PLLX*/];
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/* get osc freq */
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osc = clock_get_osc_freq();
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/* set pllx */
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sel = &tegra_pll_x_table[osc];
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if (sel->n == 0){
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return;
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}
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pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
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adjust_pllp_out_freqs();
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}
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/*
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* On poweron, AVP clock source (also called system clock) is set to PLLP_out0
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* with frequency set at 1MHz. Before initializing PLLP, we need to move the
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@ -38,6 +185,108 @@ void set_avp_clock_to_clkm(void)
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(SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
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(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
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writel(val, &clk_rst->crc_sclk_brst_pol);
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/* Wait 2-3us for the clock to flush thru the logic as per the TRM */
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udelay(3);
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udelay(2);
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}
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/**
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* The T124 requires some special clock initialization, including setting up
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* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
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*/
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void init_clocks(void)
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{
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u32 val;
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/* Set active CPU cluster to G */
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clrbits_le32(&flow->cluster_control, 1);
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/* Change the oscillator drive strength */
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val = readl(&clk_rst->crc_osc_ctrl);
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val &= ~OSC_XOFS_MASK;
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val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
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writel(val, &clk_rst->crc_osc_ctrl);
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/* Ambiguous quote from u-boot. TODO: what's this mean?
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* "should update same value in PMC_OSC_EDPD_OVER XOFS
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field for warmboot "*/
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val = readl(&pmc->pmc_osc_edpd_over);
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val &= ~PMC_XOFS_MASK;
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val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
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writel(val, &pmc->pmc_osc_edpd_over);
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/* Set HOLD_CKE_LOW_EN to 1 */
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setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
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init_pllx();
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val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
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writel(val, &clk_rst->crc_clk_sys_rate);
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/* Enable clocks to required peripherals. TBD - minimize this list */
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/* The UART is super special so Just Do It right here. */
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setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK);
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setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK);
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clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2);
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udelay(2);
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clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK);
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/* fixme. The stupidity of all this ... we are reading and
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* writing the same register lots of times when we could just
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* one lousy write with a combined mask. Sigh.
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*/
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setbits_le32(clkenable(CLK_CACHE2_REG), CLK_CACHE2_MASK);
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setbits_le32(clkenable(CLK_GPIO_REG), CLK_GPIO_MASK);
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setbits_le32(clkenable(CLK_TMR_REG), CLK_TMR_MASK);
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setbits_le32(clkenable(CLK_CPU_REG), CLK_CPU_MASK);
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setbits_le32(clkenable(CLK_EMC_REG), CLK_EMC_MASK);
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setbits_le32(clkenable(CLK_I2C1_REG), CLK_I2C1_MASK);
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setbits_le32(clkenable(CLK_I2C2_REG), CLK_I2C2_MASK);
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setbits_le32(clkenable(CLK_I2C3_REG), CLK_I2C3_MASK);
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setbits_le32(clkenable(CLK_I2C5_REG), CLK_I2C5_MASK);
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setbits_le32(clkenable(CLK_APBDMA_REG), CLK_APBDMA_MASK);
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setbits_le32(clkenable(CLK_MEM_REG), CLK_MEM_MASK);
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setbits_le32(clkenable(CLK_CSITE_REG), CLK_CSITE_MASK);
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setbits_le32(clkenablevw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK);
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setbits_le32(clkenablevw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK);
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/*
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* Set MSELECT clock source as PLLP (00)_REG, and ask for a clock
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* divider that would set the MSELECT clock at 102MHz for a
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* PLLP base of 408MHz.
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*/
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clock_ll_set_source_divisor((void *)CLK_VW_MSELECT_REG, 0,
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CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
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/* Give clock time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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/* I2C1 gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(&clk_rst->src_i2c1, 3, 16);
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/* I2C2 gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(&clk_rst->src_i2c2, 3, 16);
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/* I2C3 (cam) gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(&clk_rst->src_i2c3, 3, 16);
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/* I2C5 (PMU) gets CLK_M and a divisor of 17 */
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clock_ll_set_source_divisor(&clk_rst->src_i2c5, 3, 16);
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/* Give clock time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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/* Take required peripherals out of reset */
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clrbits_le32(clkreset(CLK_CACHE2_REG), CLK_CACHE2_MASK);
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clrbits_le32(clkreset(CLK_GPIO_REG), CLK_GPIO_MASK);
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clrbits_le32(clkreset(CLK_TMR_REG), CLK_TMR_MASK);
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clrbits_le32(clkreset(CLK_CPU_REG), CLK_CPU_MASK);
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clrbits_le32(clkreset(CLK_EMC_REG), CLK_EMC_MASK);
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clrbits_le32(clkreset(CLK_I2C5_REG), CLK_I2C5_MASK);
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clrbits_le32(clkreset(CLK_I2C3_REG), CLK_I2C3_MASK);
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clrbits_le32(clkreset(CLK_I2C2_REG), CLK_I2C2_MASK);
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clrbits_le32(clkreset(CLK_I2C1_REG), CLK_I2C1_MASK);
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clrbits_le32(clkreset(CLK_APBDMA_REG), CLK_APBDMA_MASK);
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clrbits_le32(clkreset(CLK_MEM_REG), CLK_MEM_MASK);
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clrbits_le32(clkreset(CLK_CSITE_REG), CLK_CSITE_MASK);
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clrbits_le32(clkresetvw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK);
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clrbits_le32(clkresetvw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK);
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}
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@ -17,6 +17,161 @@
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#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__
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#define __SOC_NVIDIA_TEGRA124_CLOCK_H__
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#define CLK_CONSTANTS(name, reg_index, reg_bit) \
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CLK_##name##_REG = reg_index, \
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CLK_##name##_MASK = (1 << reg_bit)
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enum {
|
||||
CLK_CONSTANTS(CPU, 0, 0),
|
||||
CLK_CONSTANTS(COP, 0, 1),
|
||||
CLK_CONSTANTS(TRIG_SYS, 0, 2),
|
||||
CLK_CONSTANTS(RTC, 0, 4),
|
||||
CLK_CONSTANTS(TMR, 0, 5),
|
||||
CLK_CONSTANTS(UARTA, 0, 6),
|
||||
CLK_CONSTANTS(UARTB, 0, 7),
|
||||
CLK_CONSTANTS(GPIO, 0, 8),
|
||||
CLK_CONSTANTS(SDMMC2, 0, 9),
|
||||
CLK_CONSTANTS(SPDIF, 0, 10),
|
||||
CLK_CONSTANTS(I2S1, 0, 11),
|
||||
CLK_CONSTANTS(I2C1, 0, 12),
|
||||
CLK_CONSTANTS(NDFLASH, 0, 13),
|
||||
CLK_CONSTANTS(SDMMC1, 0, 14),
|
||||
CLK_CONSTANTS(SDMMC4, 0, 15),
|
||||
CLK_CONSTANTS(PWM, 0, 17),
|
||||
CLK_CONSTANTS(I2S2, 0, 18),
|
||||
CLK_CONSTANTS(EPP, 0, 19),
|
||||
CLK_CONSTANTS(VI, 0, 20),
|
||||
CLK_CONSTANTS(2D, 0, 21),
|
||||
CLK_CONSTANTS(USBD, 0, 22),
|
||||
CLK_CONSTANTS(ISP, 0, 23),
|
||||
CLK_CONSTANTS(3D, 0, 24),
|
||||
CLK_CONSTANTS(DISP2, 0, 26),
|
||||
CLK_CONSTANTS(DISP1, 0, 27),
|
||||
CLK_CONSTANTS(HOST1X, 0, 28),
|
||||
CLK_CONSTANTS(VCP, 0, 29),
|
||||
CLK_CONSTANTS(I2S0, 0, 30),
|
||||
CLK_CONSTANTS(CACHE2, 0, 31),
|
||||
|
||||
CLK_CONSTANTS(MEM, 1, 0),
|
||||
CLK_CONSTANTS(AHBDMA, 1, 1),
|
||||
CLK_CONSTANTS(APBDMA, 1, 2),
|
||||
CLK_CONSTANTS(KBC, 1, 4),
|
||||
CLK_CONSTANTS(STAT_MON, 1, 5),
|
||||
CLK_CONSTANTS(PMC, 1, 6),
|
||||
CLK_CONSTANTS(FUSE, 1, 7),
|
||||
CLK_CONSTANTS(KFUSE, 1, 8),
|
||||
CLK_CONSTANTS(SBC1, 1, 9),
|
||||
CLK_CONSTANTS(SNOR, 1, 10),
|
||||
CLK_CONSTANTS(JTAG2TBC, 1, 11),
|
||||
CLK_CONSTANTS(SBC2, 1, 12),
|
||||
CLK_CONSTANTS(SBC3, 1, 14),
|
||||
CLK_CONSTANTS(I2C5, 1, 15),
|
||||
CLK_CONSTANTS(DSI, 1, 16),
|
||||
CLK_CONSTANTS(HSI, 1, 18),
|
||||
CLK_CONSTANTS(HDMI, 1, 19),
|
||||
CLK_CONSTANTS(CSI, 1, 20),
|
||||
CLK_CONSTANTS(I2C2, 1, 22),
|
||||
CLK_CONSTANTS(UARTC, 1, 23),
|
||||
CLK_CONSTANTS(MIPI_CAL, 1, 24),
|
||||
CLK_CONSTANTS(EMC, 1, 25),
|
||||
CLK_CONSTANTS(USB2, 1, 26),
|
||||
CLK_CONSTANTS(USB3, 1, 27),
|
||||
CLK_CONSTANTS(MPE, 1, 28),
|
||||
CLK_CONSTANTS(VDE, 1, 29),
|
||||
CLK_CONSTANTS(BSEA, 1, 30),
|
||||
CLK_CONSTANTS(BSEV, 1, 31),
|
||||
|
||||
CLK_CONSTANTS(UARTD, 2, 1),
|
||||
CLK_CONSTANTS(UARTE, 2, 2),
|
||||
CLK_CONSTANTS(I2C3, 2, 3),
|
||||
CLK_CONSTANTS(SBC4, 2, 4),
|
||||
CLK_CONSTANTS(SDMMC3, 2, 5),
|
||||
CLK_CONSTANTS(PCIE, 2, 6),
|
||||
CLK_CONSTANTS(OWR, 2, 7),
|
||||
CLK_CONSTANTS(AFI, 2, 8),
|
||||
CLK_CONSTANTS(CSITE, 2, 9),
|
||||
CLK_CONSTANTS(PCIEXCLK, 2, 10),
|
||||
CLK_CONSTANTS(AVPUCQ, 2, 11),
|
||||
CLK_CONSTANTS(TRACECLKIN, 2, 13),
|
||||
CLK_CONSTANTS(SOC_THERM, 2, 14),
|
||||
CLK_CONSTANTS(DTV, 2, 15),
|
||||
CLK_CONSTANTS(NAND_SPEED, 2, 16),
|
||||
CLK_CONSTANTS(I2C_SLOW, 2, 17),
|
||||
CLK_CONSTANTS(DSIB, 2, 18),
|
||||
CLK_CONSTANTS(TSEC, 2, 19),
|
||||
CLK_CONSTANTS(IRAMA, 2, 20),
|
||||
CLK_CONSTANTS(IRAMB, 2, 21),
|
||||
CLK_CONSTANTS(IRAMC, 2, 22),
|
||||
|
||||
// Clock reset.
|
||||
CLK_CONSTANTS(EMUCIF, 2, 23),
|
||||
// Clock enable.
|
||||
CLK_CONSTANTS(IRAMD, 2, 23),
|
||||
|
||||
CLK_CONSTANTS(CRAM2, 2, 24),
|
||||
CLK_CONSTANTS(XUSB_HOST, 2, 25),
|
||||
CLK_CONSTANTS(MSENC, 2, 27),
|
||||
CLK_CONSTANTS(SUS_OUT, 2, 28),
|
||||
CLK_CONSTANTS(DEV2_OUT, 2, 29),
|
||||
CLK_CONSTANTS(DEV1_OUT, 2, 30),
|
||||
CLK_CONSTANTS(XUSB_DEV, 2, 31),
|
||||
|
||||
CLK_CONSTANTS(VW_CPUG, 0, 0),
|
||||
CLK_CONSTANTS(VW_CPULP, 0, 1),
|
||||
CLK_CONSTANTS(VW_3D2, 0, 2),
|
||||
CLK_CONSTANTS(VW_MSELECT, 0, 3),
|
||||
CLK_CONSTANTS(VW_I2S3, 0, 5),
|
||||
CLK_CONSTANTS(VW_I2S4, 0, 6),
|
||||
CLK_CONSTANTS(VW_I2C4, 0, 7),
|
||||
CLK_CONSTANTS(VW_SBC5, 0, 8),
|
||||
CLK_CONSTANTS(VW_SBC6, 0, 9),
|
||||
CLK_CONSTANTS(VW_AUDIO, 0, 10),
|
||||
CLK_CONSTANTS(VW_APBIF, 0, 11),
|
||||
CLK_CONSTANTS(VW_DAM0, 0, 12),
|
||||
CLK_CONSTANTS(VW_DAM1, 0, 13),
|
||||
CLK_CONSTANTS(VW_DAM2, 0, 14),
|
||||
CLK_CONSTANTS(VW_HDA2CODEC_2X, 0, 15),
|
||||
CLK_CONSTANTS(VW_ATOMICS, 0, 16),
|
||||
CLK_CONSTANTS(VW_ACTMON, 0, 23),
|
||||
CLK_CONSTANTS(VW_SATA, 0, 28),
|
||||
CLK_CONSTANTS(VW_HDA, 0, 29),
|
||||
|
||||
CLK_CONSTANTS(VW_HDA2HDMICODEC, 1, 0),
|
||||
CLK_CONSTANTS(VW_SATACOLD, 1, 1),
|
||||
CLK_CONSTANTS(VW_CEC, 1, 8),
|
||||
CLK_CONSTANTS(VW_XUSB_PADCTL, 1, 14),
|
||||
CLK_CONSTANTS(VW_ENTROPY, 1, 21),
|
||||
CLK_CONSTANTS(VW_AMX0, 1, 25),
|
||||
CLK_CONSTANTS(VW_ADX0, 1, 26),
|
||||
CLK_CONSTANTS(VW_DVFS, 1, 27),
|
||||
CLK_CONSTANTS(VW_XUSB_SS, 1, 28),
|
||||
CLK_CONSTANTS(VW_MC1, 1, 30),
|
||||
CLK_CONSTANTS(VW_EMC1, 1, 31),
|
||||
};
|
||||
|
||||
/* PLL stabilization delay in usec */
|
||||
#define CLOCK_PLL_STABLE_DELAY_US 300
|
||||
|
||||
#define IO_STABILIZATION_DELAY (2)
|
||||
/* Calculate clock fractional divider value from ref and target frequencies */
|
||||
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
|
||||
|
||||
/* Calculate clock frequency value from reference and clock divider value */
|
||||
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
|
||||
|
||||
/* soc-specific */
|
||||
#define NVBL_PLLP_KHZ (408000)
|
||||
|
||||
/* make this a macro, rather than a function; let the C compiler find
|
||||
* the error for you if you use an out of range index.. Requires you
|
||||
* to declare a clk_rst pointer. */
|
||||
void init_pllx(void);
|
||||
#define clkreset(x) &clk_rst->crc_rst_dev[(x)]
|
||||
#define clkenable(x) &clk_rst->crc_clk_out_enb[(x)]
|
||||
#define clkresetvw(x) &clk_rst->crc_rst_dev_vw[(x)]
|
||||
#define clkenablevw(x) &clk_rst->crc_clk_out_enb_vw[(x)]
|
||||
|
||||
void set_avp_clock_to_clkm(void);
|
||||
void init_clocks(void);
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */
|
||||
|
|
|
|||
49
src/soc/nvidia/tegra124/flow.h
Normal file
49
src/soc/nvidia/tegra124/flow.h
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA124_FLOW_H_
|
||||
#define _TEGRA124_FLOW_H_
|
||||
|
||||
struct flow_ctlr {
|
||||
u32 halt_cpu_events; /* offset 0x00 */
|
||||
u32 halt_cop_events; /* offset 0x04 */
|
||||
u32 cpu_csr; /* offset 0x08 */
|
||||
u32 cop_csr; /* offset 0x0c */
|
||||
u32 xrq_events; /* offset 0x10 */
|
||||
u32 halt_cpu1_events; /* offset 0x14 */
|
||||
u32 cpu1_csr; /* offset 0x18 */
|
||||
u32 halt_cpu2_events; /* offset 0x1c */
|
||||
u32 cpu2_csr; /* offset 0x20 */
|
||||
u32 halt_cpu3_events; /* offset 0x24 */
|
||||
u32 cpu3_csr; /* offset 0x28 */
|
||||
u32 cluster_control; /* offset 0x2c */
|
||||
u32 halt_cop1_events; /* offset 0x30 */
|
||||
u32 halt_cop1_csr; /* offset 0x34 */
|
||||
u32 cpu_pwr_csr; /* offset 0x38 */
|
||||
u32 mpid; /* offset 0x3c */
|
||||
u32 ram_repair; /* offset 0x40 */
|
||||
};
|
||||
|
||||
/* HALT_COP_EVENTS_0, 0x04 */
|
||||
#define EVENT_MSEC (1 << 24)
|
||||
#define EVENT_USEC (1 << 25)
|
||||
#define EVENT_JTAG (1 << 28)
|
||||
#define EVENT_MODE_STOP (2 << 29)
|
||||
|
||||
/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
|
||||
#define ACTIVE_LP (1 << 0)
|
||||
|
||||
#endif /* _TEGRA124_FLOW_H_ */
|
||||
377
src/soc/nvidia/tegra124/pmc.h
Normal file
377
src/soc/nvidia/tegra124/pmc.h
Normal file
|
|
@ -0,0 +1,377 @@
|
|||
/*
|
||||
* Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA124_PMC_H_
|
||||
#define _TEGRA124_PMC_H_
|
||||
|
||||
/* Power Management Controller (APBDEV_PMC_) registers */
|
||||
struct pmc_ctlr {
|
||||
u32 pmc_cntrl; /* _CNTRL_0, offset 00 */
|
||||
u32 pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
|
||||
u32 pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
|
||||
u32 pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
|
||||
u32 pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
|
||||
u32 pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
|
||||
u32 pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
|
||||
u32 pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
|
||||
u32 pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
|
||||
u32 pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
|
||||
u32 pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */
|
||||
u32 pmc_clamp_status; /* _PMC_CLAMP_STATUS_0, offset 2C */
|
||||
u32 pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */
|
||||
u32 pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */
|
||||
u32 pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */
|
||||
u32 pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */
|
||||
u32 pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */
|
||||
u32 pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */
|
||||
u32 pmc_pwr_det; /* _PWR_DET_0, offset 48 */
|
||||
u32 pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */
|
||||
|
||||
u32 pmc_scratch0; /* _SCRATCH0_0, offset 50 */
|
||||
u32 pmc_scratch1; /* _SCRATCH1_0, offset 54 */
|
||||
u32 pmc_scratch2; /* _SCRATCH2_0, offset 58 */
|
||||
u32 pmc_scratch3; /* _SCRATCH3_0, offset 5C */
|
||||
u32 pmc_scratch4; /* _SCRATCH4_0, offset 60 */
|
||||
u32 pmc_scratch5; /* _SCRATCH5_0, offset 64 */
|
||||
u32 pmc_scratch6; /* _SCRATCH6_0, offset 68 */
|
||||
u32 pmc_scratch7; /* _SCRATCH7_0, offset 6C */
|
||||
u32 pmc_scratch8; /* _SCRATCH8_0, offset 70 */
|
||||
u32 pmc_scratch9; /* _SCRATCH9_0, offset 74 */
|
||||
u32 pmc_scratch10; /* _SCRATCH10_0, offset 78 */
|
||||
u32 pmc_scratch11; /* _SCRATCH11_0, offset 7C */
|
||||
u32 pmc_scratch12; /* _SCRATCH12_0, offset 80 */
|
||||
u32 pmc_scratch13; /* _SCRATCH13_0, offset 84 */
|
||||
u32 pmc_scratch14; /* _SCRATCH14_0, offset 88 */
|
||||
u32 pmc_scratch15; /* _SCRATCH15_0, offset 8C */
|
||||
u32 pmc_scratch16; /* _SCRATCH16_0, offset 90 */
|
||||
u32 pmc_scratch17; /* _SCRATCH17_0, offset 94 */
|
||||
u32 pmc_scratch18; /* _SCRATCH18_0, offset 98 */
|
||||
u32 pmc_scratch19; /* _SCRATCH19_0, offset 9C */
|
||||
u32 pmc_scratch20; /* _SCRATCH20_0, offset A0 */
|
||||
u32 pmc_scratch21; /* _SCRATCH21_0, offset A4 */
|
||||
u32 pmc_scratch22; /* _SCRATCH22_0, offset A8 */
|
||||
u32 pmc_scratch23; /* _SCRATCH23_0, offset AC */
|
||||
|
||||
u32 pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */
|
||||
u32 pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */
|
||||
u32 pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */
|
||||
u32 pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */
|
||||
u32 pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */
|
||||
u32 pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */
|
||||
|
||||
u32 pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */
|
||||
u32 pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */
|
||||
u32 pmc_pg_mask; /* _PG_MASK_0, offset D0 */
|
||||
u32 pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */
|
||||
u32 pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */
|
||||
u32 pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */
|
||||
u32 pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */
|
||||
u32 pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */
|
||||
u32 pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */
|
||||
u32 pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */
|
||||
u32 pmc_usb_ao; /* _USB_AO_0, offset F0 */
|
||||
u32 pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */
|
||||
u32 pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */
|
||||
|
||||
u32 pmc_scratch24; /* _SCRATCH24_0, offset FC */
|
||||
u32 pmc_scratch25; /* _SCRATCH24_0, offset 100 */
|
||||
u32 pmc_scratch26; /* _SCRATCH24_0, offset 104 */
|
||||
u32 pmc_scratch27; /* _SCRATCH24_0, offset 108 */
|
||||
u32 pmc_scratch28; /* _SCRATCH24_0, offset 10C */
|
||||
u32 pmc_scratch29; /* _SCRATCH24_0, offset 110 */
|
||||
u32 pmc_scratch30; /* _SCRATCH24_0, offset 114 */
|
||||
u32 pmc_scratch31; /* _SCRATCH24_0, offset 118 */
|
||||
u32 pmc_scratch32; /* _SCRATCH24_0, offset 11C */
|
||||
u32 pmc_scratch33; /* _SCRATCH24_0, offset 120 */
|
||||
u32 pmc_scratch34; /* _SCRATCH24_0, offset 124 */
|
||||
u32 pmc_scratch35; /* _SCRATCH24_0, offset 128 */
|
||||
u32 pmc_scratch36; /* _SCRATCH24_0, offset 12C */
|
||||
u32 pmc_scratch37; /* _SCRATCH24_0, offset 130 */
|
||||
u32 pmc_scratch38; /* _SCRATCH24_0, offset 134 */
|
||||
u32 pmc_scratch39; /* _SCRATCH24_0, offset 138 */
|
||||
u32 pmc_scratch40; /* _SCRATCH24_0, offset 13C */
|
||||
u32 pmc_scratch41; /* _SCRATCH24_0, offset 140 */
|
||||
u32 pmc_scratch42; /* _SCRATCH24_0, offset 144 */
|
||||
|
||||
u32 pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */
|
||||
u32 pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */
|
||||
u32 pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */
|
||||
u32 pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */
|
||||
u32 pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
|
||||
u32 pmc_gate; /* _GATE_0, offset 15C */
|
||||
u32 pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */
|
||||
u32 pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */
|
||||
u32 pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */
|
||||
u32 pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */
|
||||
u32 pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
|
||||
u32 pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */
|
||||
u32 pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */
|
||||
u32 pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */
|
||||
u32 pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */
|
||||
u32 pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */
|
||||
u32 pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */
|
||||
u32 pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */
|
||||
u32 pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */
|
||||
u32 pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */
|
||||
u32 pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */
|
||||
u32 pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */
|
||||
u32 pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */
|
||||
u32 pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */
|
||||
u32 pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */
|
||||
u32 pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */
|
||||
u32 pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */
|
||||
u32 pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */
|
||||
u32 pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */
|
||||
u32 pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */
|
||||
u32 pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */
|
||||
u32 pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */
|
||||
u32 pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */
|
||||
u32 pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */
|
||||
|
||||
u32 pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */
|
||||
u32 pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */
|
||||
u32 pmc_reserved0; /* _RESERVED, offset 1D8 */
|
||||
u32 pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
|
||||
u32 pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */
|
||||
u32 pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */
|
||||
u32 pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */
|
||||
u32 pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
|
||||
u32 pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
|
||||
u32 pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */
|
||||
u32 pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
|
||||
u32 pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
|
||||
|
||||
u32 pmc_todo_0[9]; /* offset 200-220 */
|
||||
u32 pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */
|
||||
u32 pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */
|
||||
u32 pmc_scratch43; /* _SCRATCH43_0, offset 22C */
|
||||
u32 pmc_scratch44; /* _SCRATCH44_0, offset 230 */
|
||||
u32 pmc_scratch45;
|
||||
u32 pmc_scratch46;
|
||||
u32 pmc_scratch47;
|
||||
u32 pmc_scratch48;
|
||||
u32 pmc_scratch49;
|
||||
u32 pmc_scratch50;
|
||||
u32 pmc_scratch51;
|
||||
u32 pmc_scratch52;
|
||||
u32 pmc_scratch53;
|
||||
u32 pmc_scratch54;
|
||||
u32 pmc_scratch55; /* _SCRATCH55_0, offset 25C */
|
||||
u32 pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */
|
||||
u32 pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */
|
||||
u32 pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */
|
||||
u32 pmc_todo_1[17]; /* TODO: 26C ~ 2AC */
|
||||
u32 pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */
|
||||
u32 pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */
|
||||
u32 pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
|
||||
u32 pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */
|
||||
u32 pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */
|
||||
u32 pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */
|
||||
u32 pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */
|
||||
u32 pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */
|
||||
u32 pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */
|
||||
u32 pmc_secure_scratch9;
|
||||
u32 pmc_secure_scratch10;
|
||||
u32 pmc_secure_scratch11;
|
||||
u32 pmc_secure_scratch12;
|
||||
u32 pmc_secure_scratch13;
|
||||
u32 pmc_secure_scratch14;
|
||||
u32 pmc_secure_scratch15;
|
||||
u32 pmc_secure_scratch16;
|
||||
u32 pmc_secure_scratch17;
|
||||
u32 pmc_secure_scratch18;
|
||||
u32 pmc_secure_scratch19;
|
||||
u32 pmc_secure_scratch20;
|
||||
u32 pmc_secure_scratch21;
|
||||
u32 pmc_secure_scratch22;
|
||||
u32 pmc_secure_scratch23;
|
||||
u32 pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */
|
||||
u32 pmc_secure_scratch25;
|
||||
u32 pmc_secure_scratch26;
|
||||
u32 pmc_secure_scratch27;
|
||||
u32 pmc_secure_scratch28;
|
||||
u32 pmc_secure_scratch29;
|
||||
u32 pmc_secure_scratch30;
|
||||
u32 pmc_secure_scratch31;
|
||||
u32 pmc_secure_scratch32;
|
||||
u32 pmc_secure_scratch33;
|
||||
u32 pmc_secure_scratch34;
|
||||
u32 pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */
|
||||
|
||||
u32 pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */
|
||||
u32 pmc_cntrl2; /* _CNTRL2_0, offset 440 */
|
||||
u32 pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */
|
||||
u32 pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */
|
||||
u32 pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */
|
||||
u32 pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */
|
||||
u32 pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */
|
||||
|
||||
u32 pmc_scratch56; /* _SCRATCH56_0, offset 600 */
|
||||
u32 pmc_scratch57;
|
||||
u32 pmc_scratch58;
|
||||
u32 pmc_scratch59;
|
||||
u32 pmc_scratch60;
|
||||
u32 pmc_scratch61;
|
||||
u32 pmc_scratch62;
|
||||
u32 pmc_scratch63;
|
||||
u32 pmc_scratch64;
|
||||
u32 pmc_scratch65;
|
||||
u32 pmc_scratch66;
|
||||
u32 pmc_scratch67;
|
||||
u32 pmc_scratch68;
|
||||
u32 pmc_scratch69;
|
||||
u32 pmc_scratch70;
|
||||
u32 pmc_scratch71;
|
||||
u32 pmc_scratch72;
|
||||
u32 pmc_scratch73;
|
||||
u32 pmc_scratch74;
|
||||
u32 pmc_scratch75;
|
||||
u32 pmc_scratch76;
|
||||
u32 pmc_scratch77;
|
||||
u32 pmc_scratch78;
|
||||
u32 pmc_scratch79;
|
||||
u32 pmc_scratch80;
|
||||
u32 pmc_scratch81;
|
||||
u32 pmc_scratch82;
|
||||
u32 pmc_scratch83;
|
||||
u32 pmc_scratch84;
|
||||
u32 pmc_scratch85;
|
||||
u32 pmc_scratch86;
|
||||
u32 pmc_scratch87;
|
||||
u32 pmc_scratch88;
|
||||
u32 pmc_scratch89;
|
||||
u32 pmc_scratch90;
|
||||
u32 pmc_scratch91;
|
||||
u32 pmc_scratch92;
|
||||
u32 pmc_scratch93;
|
||||
u32 pmc_scratch94;
|
||||
u32 pmc_scratch95;
|
||||
u32 pmc_scratch96;
|
||||
u32 pmc_scratch97;
|
||||
u32 pmc_scratch98;
|
||||
u32 pmc_scratch99;
|
||||
u32 pmc_scratch100;
|
||||
u32 pmc_scratch101;
|
||||
u32 pmc_scratch102;
|
||||
u32 pmc_scratch103;
|
||||
u32 pmc_scratch104;
|
||||
u32 pmc_scratch105;
|
||||
u32 pmc_scratch106;
|
||||
u32 pmc_scratch107;
|
||||
u32 pmc_scratch108;
|
||||
u32 pmc_scratch109;
|
||||
u32 pmc_scratch110;
|
||||
u32 pmc_scratch111;
|
||||
u32 pmc_scratch112;
|
||||
u32 pmc_scratch113;
|
||||
u32 pmc_scratch114;
|
||||
u32 pmc_scratch115;
|
||||
u32 pmc_scratch116;
|
||||
u32 pmc_scratch117;
|
||||
u32 pmc_scratch118;
|
||||
u32 pmc_scratch119;
|
||||
u32 pmc_scratch1_eco; /* offset 700 */
|
||||
};
|
||||
|
||||
#define CPU_PWRED 1
|
||||
#define CPU_CLMP 1
|
||||
|
||||
#define PARTID_CP 0xFFFFFFF8
|
||||
#define START_CP (1 << 8)
|
||||
|
||||
#define CPUPWRREQ_OE (1 << 16)
|
||||
#define CPUPWRREQ_POL (1 << 15)
|
||||
|
||||
#define CRAILID (0)
|
||||
#define CE0ID (14)
|
||||
#define C0NCID (15)
|
||||
#define CRAIL (1 << CRAILID)
|
||||
#define CE0 (1 << CE0ID)
|
||||
#define C0NC (1 << C0NCID)
|
||||
|
||||
#define PMC_XOFS_SHIFT 1
|
||||
#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
|
||||
|
||||
#define TIMER_MULT_SHIFT 0
|
||||
#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
|
||||
#define TIMER_MULT_CPU_SHIFT 2
|
||||
#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
|
||||
#define MULT_1 0
|
||||
#define MULT_2 1
|
||||
#define MULT_4 2
|
||||
#define MULT_8 3
|
||||
|
||||
#define AMAP_WRITE_SHIFT 20
|
||||
#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
|
||||
|
||||
/* SEC_DISABLE_0, 0x04 */
|
||||
#define SEC_DISABLE_WRITE0_ON (1 << 4)
|
||||
#define SEC_DISABLE_READ0_ON (1 << 5)
|
||||
#define SEC_DISABLE_WRITE1_ON (1 << 6)
|
||||
#define SEC_DISABLE_READ1_ON (1 << 7)
|
||||
#define SEC_DISABLE_WRITE2_ON (1 << 8)
|
||||
#define SEC_DISABLE_READ2_ON (1 << 9)
|
||||
#define SEC_DISABLE_WRITE3_ON (1 << 10)
|
||||
#define SEC_DISABLE_READ3_ON (1 << 11)
|
||||
#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20)
|
||||
|
||||
/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
|
||||
#define PWRGATE_TOGGLE_PARTID_CRAIL 0
|
||||
#define PWRGATE_TOGGLE_PARTID_TD 1
|
||||
#define PWRGATE_TOGGLE_PARTID_VE 2
|
||||
#define PWRGATE_TOGGLE_PARTID_VDE 4
|
||||
#define PWRGATE_TOGGLE_PARTID_L2C 5
|
||||
#define PWRGATE_TOGGLE_PARTID_MPE 6
|
||||
#define PWRGATE_TOGGLE_PARTID_HEG 7
|
||||
#define PWRGATE_TOGGLE_PARTID_CE1 9
|
||||
#define PWRGATE_TOGGLE_PARTID_CE2 10
|
||||
#define PWRGATE_TOGGLE_PARTID_CE3 11
|
||||
#define PWRGATE_TOGGLE_PARTID_CELP 12
|
||||
#define PWRGATE_TOGGLE_PARTID_CE0 14
|
||||
#define PWRGATE_TOGGLE_PARTID_C0NC 15
|
||||
#define PWRGATE_TOGGLE_PARTID_C1NC 16
|
||||
#define PWRGATE_TOGGLE_PARTID_DIS 18
|
||||
#define PWRGATE_TOGGLE_PARTID_DISB 19
|
||||
#define PWRGATE_TOGGLE_PARTID_XUSBA 20
|
||||
#define PWRGATE_TOGGLE_PARTID_XUSBB 21
|
||||
#define PWRGATE_TOGGLE_PARTID_XUSBC 22
|
||||
#define PWRGATE_TOGGLE_START (1 << 8)
|
||||
|
||||
/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
|
||||
#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0)
|
||||
#define PWRGATE_STATUS_TD_ENABLE (1 << 1)
|
||||
#define PWRGATE_STATUS_VE_ENABLE (1 << 2)
|
||||
#define PWRGATE_STATUS_VDE_ENABLE (1 << 4)
|
||||
#define PWRGATE_STATUS_L2C_ENABLE (1 << 5)
|
||||
#define PWRGATE_STATUS_MPE_ENABLE (1 << 6)
|
||||
#define PWRGATE_STATUS_HEG_ENABLE (1 << 7)
|
||||
#define PWRGATE_STATUS_CE1_ENABLE (1 << 9)
|
||||
#define PWRGATE_STATUS_CE2_ENABLE (1 << 10)
|
||||
#define PWRGATE_STATUS_CE3_ENABLE (1 << 11)
|
||||
#define PWRGATE_STATUS_CELP_ENABLE (1 << 12)
|
||||
#define PWRGATE_STATUS_CE0_ENABLE (1 << 14)
|
||||
#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15)
|
||||
#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16)
|
||||
#define PWRGATE_STATUS_DIS_ENABLE (1 << 18)
|
||||
#define PWRGATE_STATUS_DISB_ENABLE (1 << 19)
|
||||
#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20)
|
||||
#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21)
|
||||
#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22)
|
||||
|
||||
/* APBDEV_PMC_CNTRL2_0 0x440 */
|
||||
#define HOLD_CKE_LOW_EN (1 << 12)
|
||||
|
||||
#endif /* _TEGRA124_PMC_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue