broadwell: Unify chip.h and add chip.c
Pull together all the used register definitions from the cpu/northbridge/southbridge chip.h files into one structure for the broadwell SOC. Add a chip.c file that contains the main chip_operations structure as well as a shared pci_operations structure that can be used by other ramstage drivers. The chip broadwell_enable function handles different bus types and splits the work out to the right subsystem. BUG=chrome-os-partner:28234 TEST=None Change-Id: I42ceed278b3cd5c46c2384c3f6528246a2193cc8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198917 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
abb5f87e54
commit
a9c2d7ff3a
3 changed files with 197 additions and 87 deletions
82
src/soc/intel/broadwell/chip.c
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82
src/soc/intel/broadwell/chip.c
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@ -0,0 +1,82 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/ramstage.h>
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#include <chip.h>
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_ops_mmconf,
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};
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static void cpu_bus_noop(device_t dev) { }
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static struct device_operations cpu_bus_ops = {
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.read_resources = &cpu_bus_noop,
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.set_resources = &cpu_bus_noop,
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.enable_resources = &cpu_bus_noop,
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.init = &broadwell_init_cpus,
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};
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static void broadwell_enable(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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/* Handle PCH device enable */
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if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD &&
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(dev->ops == NULL || dev->ops->enable == NULL)) {
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broadwell_pch_enable_dev(dev);
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}
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}
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}
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struct chip_operations soc_intel_broadwell_ops = {
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CHIP_NAME("Intel Broadwell")
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.enable_dev = &broadwell_enable,
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.init = &broadwell_init_pre_device,
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};
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device)
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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else
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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(device << 16) | vendor);
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}
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struct pci_operations broadwell_pci_ops = {
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.set_subsystem = &pci_set_subsystem
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};
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@ -18,27 +18,120 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* Digital Port Hotplug Enable:
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* 0x04 = Enabled, 2ms short pulse
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* 0x05 = Enabled, 4.5ms short pulse
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* 0x06 = Enabled, 6ms short pulse
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* 0x07 = Enabled, 100ms short pulse
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*/
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struct northbridge_intel_haswell_config {
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u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
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u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
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u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
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#ifndef _SOC_INTEL_BROADWELL_CHIP_H_
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#define _SOC_INTEL_BROADWELL_CHIP_H_
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u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
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u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
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u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
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u16 gpu_panel_power_down_delay; /* T3 time sequence */
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u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
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u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
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struct soc_intel_broadwell_config {
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/*
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
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u32 gpu_pch_backlight; /* PCH Backlight PWM value */
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/* GPE configuration */
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uint32_t gpe0_en_1;
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uint32_t gpe0_en_2;
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uint32_t gpe0_en_3;
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uint32_t gpe0_en_4;
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/* GPIO SMI configuration */
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uint32_t alt_gp_smi_en;
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/* IDE configuration */
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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/*
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* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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uint8_t sata_devslp_mux;
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/*
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* DEVSLP Disable
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* 0: DEVSLP is enabled
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* 1: DEVSLP is disabled
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*/
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uint8_t sata_devslp_disable;
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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uint8_t pcie_port_coalesce;
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/* Force root port ASPM configuration with port bitmap */
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uint8_t pcie_port_force_aspm;
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/* Put SerialIO devices into ACPI mode instead of a PCI device */
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uint8_t sio_acpi_mode;
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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/*
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* Clock Disable Map:
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* [21:16] = CLKOUT_PCIE# 5-0
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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/*
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* Digital Port Hotplug Enable:
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* 0x04 = Enabled, 2ms short pulse
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* 0x05 = Enabled, 4.5ms short pulse
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* 0x06 = Enabled, 6ms short pulse
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* 0x07 = Enabled, 100ms short pulse
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*/
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u8 gpu_dp_b_hotplug;
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u8 gpu_dp_c_hotplug;
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u8 gpu_dp_d_hotplug;
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/* Panel power sequence timings */
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u8 gpu_panel_port_select;
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u8 gpu_panel_power_cycle_delay;
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u16 gpu_panel_power_up_delay;
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u16 gpu_panel_power_down_delay;
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u16 gpu_panel_power_backlight_on_delay;
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u16 gpu_panel_power_backlight_off_delay;
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/* Panel backlight settings */
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u32 gpu_cpu_backlight;
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u32 gpu_pch_backlight;
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/*
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* Graphics CD Clock Frequency
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* 0 = 337.5MHz
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* 1 = 450MHz
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* 2 = 540MHz
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* 3 = 675MHz
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*/
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int cdclk;
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/* Enable S0iX support */
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int s0ix_enable;
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/* TCC activation offset */
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int tcc_offset;
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};
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extern struct chip_operations northbridge_intel_haswell_ops;
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typedef struct soc_intel_broadwell_config config_t;
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extern struct chip_operations soc_ops;
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#endif
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@ -69,28 +69,6 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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return 0;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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}
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/* TODO We could determine how many PCIe busses we need in
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* the bar. For now that number is hardcoded to a max of 64.
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* See e7525/northbridge.c for an example.
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*/
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = NULL,
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.init = NULL,
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.scan_bus = pci_domain_scan_bus,
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#if CONFIG_MMCONF_SUPPORT_DEFAULT
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.ops_pci_bus = &pci_ops_mmconf,
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#else
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.ops_pci_bus = &pci_cf8_conf1,
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#endif
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};
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static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 bar;
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@ -497,46 +475,3 @@ static struct device_operations mc_ops = {
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.ops_pci = &intel_pci_ops,
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};
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static const struct pci_driver mc_driver_hsw_mobile __pci_driver = {
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_HSW_MOBILE,
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};
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static const struct pci_driver mc_driver_hsw_ult __pci_driver = {
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_HSW_ULT,
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};
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static void cpu_bus_init(device_t dev)
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{
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bsp_init_and_start_aps(dev->link_list);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(device_t dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_haswell_ops = {
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CHIP_NAME("Intel i7 (Haswell) integrated Northbridge")
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.enable_dev = enable_dev,
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};
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