broadwell: Remove old pei_data and add cpu function for romstage
- The old pei_data structure from haswell was still present - Add a function for romstage to read CPU family/model - Add quick_ram_check after memory init BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 with broadwell CPU Change-Id: I48ae199351d383796b28197fc0368770cba80ec4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/201690 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
8ecd9d2096
commit
d206c9cdd6
3 changed files with 10 additions and 115 deletions
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@ -1,115 +0,0 @@
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/*
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* coreboot UEFI PEI wrapper
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*
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* Copyright (c) 2011, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Google Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef PEI_DATA_H
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#define PEI_DATA_H
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typedef void (*tx_byte_func)(unsigned char byte);
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#define PEI_VERSION 15
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#define MAX_USB2_PORTS 16
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#define MAX_USB3_PORTS 16
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_BACK_PANEL = 0,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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USB_PORT_SKIP
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};
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/* Usb Port Length:
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* [16:4] = length in inches in octal format
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* [3:0] = decimal point
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*/
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struct usb2_port_setting {
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uint16_t length;
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uint8_t enable;
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uint8_t over_current_pin;
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uint8_t location;
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} __attribute__((packed));
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struct usb3_port_setting {
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uint8_t enable;
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uint8_t over_current_pin;
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} __attribute__((packed));
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struct pei_data
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{
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uint32_t pei_version;
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uint32_t mchbar;
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uint32_t dmibar;
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uint32_t epbar;
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uint32_t pciexbar;
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uint16_t smbusbar;
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uint32_t wdbbar;
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uint32_t wdbsize;
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uint32_t hpet_address;
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uint32_t rcba;
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uint32_t pmbase;
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uint32_t gpiobase;
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uint32_t temp_mmio_base;
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uint32_t system_type; // 0 Mobile, 1 Desktop/Server
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uint32_t tseg_size;
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uint8_t spd_addresses[4];
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int boot_mode;
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int ec_present;
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int gbe_enable;
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Enable 2x Refresh Mode */
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int ddr_refresh_2x;
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int dq_pins_interleaved;
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/* Data read from flash and passed into MRC */
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unsigned char *mrc_input;
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unsigned int mrc_input_len;
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/* Data from MRC that should be saved to flash */
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unsigned char *mrc_output;
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unsigned int mrc_output_len;
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/*
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* Max frequency DDR3 could be ran at. Could be one of four values: 800,
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* 1067, 1333, 1600
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*/
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uint32_t max_ddr3_freq;
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/* Route all USB ports to XHCI controller in resume path */
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int usb_xhci_on_resume;
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
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uint8_t spd_data[4][256];
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tx_byte_func tx_byte;
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} __attribute__((packed));
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#endif
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@ -17,6 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/cpu.h>
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#include <stdlib.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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@ -24,6 +25,11 @@
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#include <broadwell/msr.h>
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#include <broadwell/romstage.h>
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u32 cpu_family_model(void)
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{
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return cpuid_eax(1) & 0x0fff0ff0;
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}
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void set_max_freq(void)
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{
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msr_t msr, perf_ctl, platform_info;
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@ -24,6 +24,7 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <lib.h>
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#include <string.h>
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#if CONFIG_EC_GOOGLE_CHROMEEC
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#include <ec/google/chromeec/ec.h>
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@ -95,6 +96,9 @@ void raminit(struct pei_data *pei_data)
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report_memory_config();
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/* Basic memory sanity test */
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quick_ram_check();
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if (pei_data->boot_mode != SLEEP_STATE_S3) {
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cbmem_initialize_empty();
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} else if (cbmem_initialize()) {
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