broadwell: Update and unify the finalize steps
- Move all of the finalize steps from cpu/northbridge/southbridge into this one file and convert it to (largely) use reg_script format. - Add a BOOT_STATE_INIT_ENTRY to have this function called as the last step before boot and resume instead of triggering it from SMI. - Re-initialize the SPI controller after lockdown so it still works. - Issue IO write to finalize SMM which will tell SMM to re-init SPI controller driver after lockdown. BUG=chrome-os-partner:28234 TEST=None Change-Id: I0ef6506954c193ae668b26ed10160ad4852af5e2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199390 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
3f25c23dc5
commit
ddc4c116b4
2 changed files with 118 additions and 27 deletions
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@ -18,38 +18,110 @@
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*/
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#include <arch/io.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <stdlib.h>
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#include "haswell.h"
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#include <broadwell/pci_devs.h>
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#include <broadwell/lpc.h>
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#include <broadwell/me.h>
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#include <broadwell/rcba.h>
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#include <broadwell/spi.h>
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#include <broadwell/systemagent.h>
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#define PCI_DEV_HSW PCI_DEV(0, 0, 0)
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const struct reg_script system_agent_finalize_script[] = {
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REG_PCI_OR16(0x50, 1 << 0), /* GGC */
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REG_PCI_OR32(0x5c, 1 << 0), /* DPR */
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REG_PCI_OR32(0x78, 1 << 10), /* ME */
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REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */
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REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */
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REG_PCI_OR32(0xa0, 1 << 0), /* TOM */
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REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */
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REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */
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REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */
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REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */
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REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
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REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
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REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
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void intel_northbridge_haswell_finalize_smm(void)
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REG_SCRIPT_END
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};
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const struct reg_script pch_finalize_script[] = {
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/* Set SPI opcode menu */
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
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SPI_OPPREFIX),
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
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SPI_OPTYPE),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
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SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
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/* Lock SPIBAR */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
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SPIBAR_HSFS_FLOCKDN),
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/* TC Lockdown */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
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/* BIOS Interface Lockdown */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
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/* Function Disable SUS Well Lockdown */
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REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
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/* Global SMI Lock */
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REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
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/* GEN_PMCON Lock */
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REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
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/* PMSYNC */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
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REG_SCRIPT_END
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};
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static void broadwell_finalize(void *unused)
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{
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pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */
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pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */
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pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */
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pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */
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pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */
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pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */
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pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */
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pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */
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pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */
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pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */
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pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
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MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
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MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */
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MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */
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MCHBAR32_OR(0x6800, 1 << 31);
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MCHBAR32_OR(0x7000, 1 << 31);
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MCHBAR32_OR(0x77fc, 1 << 0);
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reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
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reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
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/* Memory Controller Lockdown */
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MCHBAR8(0x50fc) = 0x8f;
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/* Read+write the following */
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/* Read+Write the following registers */
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MCHBAR32(0x6030) = MCHBAR32(0x6030);
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MCHBAR32(0x6034) = MCHBAR32(0x6034);
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MCHBAR32(0x6008) = MCHBAR32(0x6008);
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RCBA32(0x21a4) = RCBA32(0x21a4);
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/* Re-init SPI after lockdown */
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spi_init();
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/* Lock down management engine */
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intel_me_finalize();
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRIES(finalize) = {
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
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broadwell_finalize, NULL),
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
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broadwell_finalize, NULL),
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};
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@ -269,6 +269,22 @@ static void southbridge_smi_gsmi(void)
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}
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#endif
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static void finalize(void)
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{
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static int finalize_done;
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if (finalize_done) {
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printk(BIOS_DEBUG, "SMM already finalized.\n");
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return;
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}
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finalize_done = 1;
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#if CONFIG_SPI_FLASH_SMM
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/* Re-init SPI driver to handle locked BAR */
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spi_init();
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#endif
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}
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static void southbridge_smi_apmc(void)
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{
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u8 reg8;
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@ -300,6 +316,9 @@ static void southbridge_smi_apmc(void)
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enable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_FINALIZE:
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finalize();
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break;
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case APM_CNT_GNVS_UPDATE:
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if (smm_initialized) {
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printk(BIOS_DEBUG,
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