broadwell: Create iomap.h header with platform base addresses

Instead of having various defined base addresses in different
headers put them all in one well defined location.  The names
are changed to be more consistent with baytrail implementation.

Some defines are for early temporary base addresses, a few of
which are taken from Kconfig variables and are set here in order
to be consistent with the ones that are not defined in Kconfig.

The code will be changed to use the new defines in subsequent
commits.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I315d8c6f4188244bc86342e8c5dce60924653c58
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198736
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/broadwell/broadwell/iomap.h

@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_IOMAP_H_
+#define _BROADWELL_IOMAP_H_
+
+#define MCFG_BASE_ADDRESS	CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE		0x4000000
+
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+
+#define DMI_BASE_ADDRESS	0xfed18000
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_ADDRESS		0xfed19000
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_ADDRESS	0xfed80000
+#define EDRAM_BASE_SIZE		0x4000
+
+#define GDXC_BASE_ADDRESS	0xfed84000
+#define GDXC_BASE_SIZE		0x1000
+
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x4000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define ACPI_BASE_ADDRESS	0x1000
+#define ACPI_BASE_SIZE		0x100
+
+#define GPIO_BASE_ADDRESS	0x1400
+#define GPIO_BASE_SIZE		0x400
+
+#define SMBUS_BASE_ADDRESS	0x0400
+#define SMBUS_BASE_SIZE		0x10
+
+/* Temporary addresses used in romstage */
+#define EARLY_GTT_BAR		0xe0000000
+#define EARLY_XHCI_BAR		0xd7000000
+#define EARLY_EHCI_BAR		CONFIG_EHCI_BAR
+#define EARLY_UART_BAR		CONFIG_TTYS0_BASE
+#define EARLY_TEMP_MMIO		0xfed08000
+
+#endif

src/soc/intel/broadwell/broadwell/pch.h

@@ -61,30 +61,6 @@
 #define LPT_LP_STEP_B1		0x03
 #define LPT_LP_STEP_B2		0x04
 
-/*
- * It does not matter where we put the SMBus I/O base, as long as we
- * keep it consistent and don't interfere with other devices.  Stage2
- * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
- * again. But handling static BARs is a generic problem that should be
- * solved in the device allocator.
- */
-#define SMBUS_IO_BASE		0x0400
-#define SMBUS_SLAVE_ADDR	0x24
-
-#if CONFIG_INTEL_LYNXPOINT_LP
-#define DEFAULT_PMBASE		0x1000
-#define DEFAULT_GPIOBASE	0x1400
-#define DEFAULT_GPIOSIZE	0x400
-#else
-#define DEFAULT_PMBASE		0x500
-#define DEFAULT_GPIOBASE	0x480
-#define DEFAULT_GPIOSIZE	0x80
-#endif
-
-#define HPET_ADDR		0xfed00000
-#define DEFAULT_RCBA		0xfed1c000
-
 #ifndef __ACPI__
 
 #if defined (__SMM__) && !defined(__ASSEMBLER__)
@@ -154,11 +130,6 @@ void pch_enable_lpc(void);
 #define PCH_ME_DEV		PCI_DEV(0, 0x16, 0)
 #define PCH_PCIE_DEV_SLOT	28
 
-/* Southbridge IO BARs */
-
-#define GPIOBASE		0x48
-
-#define PMBASE		0x40
 
 #endif /* __ACPI__ */
 #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */

src/soc/intel/broadwell/broadwell/systemagent.h

@@ -29,11 +29,6 @@
 /* Intel Enhanced Debug region */
 #define IED_SIZE	CONFIG_IED_REGION_SIZE
 
-/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
-#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
-#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
-#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 
 #include <southbridge/intel/lynxpoint/pch.h>