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baytrail: Change all GPIO related pull resistors from 10K to 20K

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Change all pull down and pull up resistors from 10K to 20K,
it will save more power on various rails.

BUG=chrome-os-partner:24583
BRANCH=baytrail
TEST=build and boot on rambi, use modified kernel driver to execute

Change-Id: Id588bd9ac4dc71d0783ab933c15ecda0abdadad0
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/187570
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
This commit is contained in:
Kein Yuan 2014-02-22 12:26:55 -08:00 • committed by chrome-internal-fetch
commit 762e99861d
1 changed files with 27 additions and 13 deletions
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40
src/soc/intel/baytrail/baytrail/gpio.h
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@ -163,6 +163,13 @@
.use_sel = GPIO_USE_MMIO, \
.is_gpio = 1 }
#define GPIO_INPUT_PU_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \
.use_sel = GPIO_USE_MMIO, \
.is_gpio = 1 }
#define GPIO_INPUT_PD_10K \
{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
@ -170,15 +177,22 @@
.use_sel = GPIO_USE_MMIO, \
.is_gpio = 1 }
#define GPIO_INPUT_PD_20K \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \
.use_sel = GPIO_USE_MMIO, \
.is_gpio = 1 }
#define GPIO_INPUT_NOPU \
{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \
.use_sel = GPIO_USE_MMIO, \
.is_gpio = 1 }
#define GPIO_INPUT_LEGACY_NOPU \
{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \
.use_sel = GPIO_USE_LEGACY, \
@ -187,7 +201,7 @@
/* Direct / dedicated IRQ input - pass signal directly to apic */
#define GPIO_DIRQ \
{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, }
@ -220,13 +234,13 @@
.pad_val = PAD_VAL_DEFAULT }
/* Default functional configs -- no PU */
#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K)
#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K)
#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K)
#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K)
#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K)
#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K)
#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K)
#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K)
#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K)
#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K)
#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K)
#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K)
#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K)
#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K)
/* ACPI GPIO routing. Assume everything is externally pulled and negative edge
* triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */
@ -265,9 +279,9 @@
/* Common default GPIO settings */
#define GPIO_INPUT GPIO_INPUT_NOPU
#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
#define GPIO_INPUT_PU GPIO_INPUT_PU_10K
#define GPIO_INPUT_PD GPIO_INPUT_PD_10K
#define GPIO_NC GPIO_INPUT_PU_10K
#define GPIO_INPUT_PU GPIO_INPUT_PU_20K
#define GPIO_INPUT_PD GPIO_INPUT_PD_20K
#define GPIO_NC GPIO_INPUT_PU_20K
#define GPIO_DEFAULT GPIO_FUNC0
/* 16 DirectIRQs per supported bank */