tegra124: strict error detection and reporting for SPI
This re-factors the SPI driver to be more pedantic about spotting errors and reporting them. BUG=none BRANCH=none TEST=tested on nyan Change-Id: Ice51ff67b15c677826a201f2e35afe9707708b03 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173681 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
David Hendricks
chrome-internal-fetch
parent
4a9b7b47b3
commit
c056fa954e
1 changed files with 111 additions and 47 deletions
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@ -250,7 +250,7 @@ void spi_cs_deactivate(struct spi_slave *slave)
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write32(val, ®s->command1);
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}
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static void print_fifo_status(struct tegra_spi_channel *spi)
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static void dump_fifo_status(struct tegra_spi_channel *spi)
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{
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u32 status = read32(&spi->regs->fifo_status);
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@ -316,69 +316,121 @@ static void dump_dma_regs(struct apb_dma_channel *dma)
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read32(&dma->regs->word_transfer));
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}
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static void dump_regs(struct tegra_spi_channel *spi,
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struct apb_dma_channel *dma)
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{
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if (dma)
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dump_dma_regs(dma);
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if (spi) {
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dump_spi_regs(spi);
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dump_fifo_status(spi);
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}
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}
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static int fifo_error(struct tegra_spi_channel *spi)
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{
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return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0;
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}
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static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi)
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{
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/* FIXME: Make this take total packet size into account */
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return read32(&spi->regs->trans_status) &
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(SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT);
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}
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static int tegra_spi_fifo_receive(struct tegra_spi_channel *spi,
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u8 *din, unsigned int in_bytes)
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{
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unsigned int remaining;
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unsigned int received = 0, remaining = in_bytes;
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printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes);
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setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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while (in_bytes) {
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remaining = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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in_bytes -= remaining;
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while (remaining) {
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unsigned int from_fifo;
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from_fifo = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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remaining -= from_fifo;
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/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
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* PIO transfers */
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write32(remaining - 1, &spi->regs->dma_blk);
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write32(from_fifo - 1, &spi->regs->dma_blk);
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != remaining)
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;
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/* FIXME: delay loops should be "thread" friendly */
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while (spi_byte_count(spi) != from_fifo) {
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if (fifo_error(spi))
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goto done;
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}
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while (remaining) {
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received += from_fifo;
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while (from_fifo) {
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*din = read8(&spi->regs->rx_fifo);
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din++;
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remaining--;
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from_fifo--;
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}
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}
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done:
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clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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if ((received != in_bytes) || fifo_error(spi)) {
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printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n",
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__func__, received, in_bytes);
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dump_regs(spi, NULL);
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return -1;
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}
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return in_bytes;
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}
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static int tegra_spi_fifo_send(struct tegra_spi_channel *spi,
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const u8 *dout, unsigned int out_bytes)
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{
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unsigned int remaining;
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unsigned int sent = 0, remaining = out_bytes;
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printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes);
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setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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while (out_bytes) {
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remaining = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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out_bytes -= remaining;
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while (remaining) {
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unsigned int to_fifo, tmp;
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to_fifo = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
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* PIO transfers */
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write32(remaining - 1, &spi->regs->dma_blk);
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write32(to_fifo - 1, &spi->regs->dma_blk);
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while (remaining) {
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tmp = to_fifo;
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while (tmp) {
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write32(*dout, &spi->regs->tx_fifo);
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dout++;
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remaining--;
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tmp--;
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}
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
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/* FIXME: delay loops should be "thread" friendly */
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while (!(read32(&spi->regs->fifo_status) &
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SPI_FIFO_STATUS_TX_FIFO_EMPTY))
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;
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SPI_FIFO_STATUS_TX_FIFO_EMPTY)) {
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if (fifo_error(spi))
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goto done;
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}
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remaining -= to_fifo;
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sent += to_fifo;
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}
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done:
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clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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if ((sent != out_bytes) || fifo_error(spi)) {
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printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected "
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"to send %u\n", __func__, sent, out_bytes);
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dump_regs(spi, NULL);
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return -1;
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}
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return out_bytes;
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}
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@ -450,8 +502,7 @@ static int tegra_spi_dma_receive(struct tegra_spi_channel *spi,
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dma_start(dma);
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/* FIXME: delay loops should be "thread" friendly */
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != in_bytes)
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while (spi_byte_count(spi) != in_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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@ -461,8 +512,12 @@ static int tegra_spi_dma_receive(struct tegra_spi_channel *spi,
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dma_stop(dma);
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dma_release(dma);
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR)
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dump_dma_regs(dma);
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if ((spi_byte_count(spi) != in_bytes) || fifo_error(spi)) {
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printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n",
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__func__, spi_byte_count(spi), in_bytes);
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dump_regs(spi, dma);
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return -1;
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}
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return in_bytes;
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}
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@ -508,15 +563,18 @@ static int tegra_spi_dma_send(struct tegra_spi_channel *spi,
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dma_busy(dma))
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;
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dma_stop(dma);
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != out_bytes)
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while (spi_byte_count(spi) != out_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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dma_release(dma);
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR)
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dump_dma_regs(dma);
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if ((spi_byte_count(spi) != out_bytes) || fifo_error(spi)) {
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printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected %u\n",
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__func__, spi_byte_count(spi), out_bytes);
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dump_regs(spi, dma);
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return -1;
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}
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return out_bytes;
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}
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@ -540,7 +598,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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/*
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* DMA operates on 4 bytes at a time, so to avoid accessing memory
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* outside the specified buffers we'll only use DMA for 4-byte aligned
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* transactions accesses and transfer remaining bytes using FIFO access.
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* transactions accesses and transfer remaining bytes manually using
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* the Rx/Tx FIFOs.
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*/
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while (out_bytes > 0) {
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@ -551,20 +610,23 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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dma_out -= fifo_out;
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if (dma_out) {
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tegra_spi_dma_send(spi, out_buf, dma_out);
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ret = tegra_spi_dma_send(spi, out_buf, dma_out);
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if (ret != dma_out) {
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ret = -1;
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goto spi_xfer_exit;
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}
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out_buf += dma_out;
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out_bytes -= dma_out;
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}
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if (fifo_out) {
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tegra_spi_fifo_send(spi, out_buf, fifo_out);
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ret = tegra_spi_fifo_send(spi, out_buf, fifo_out);
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if (ret != fifo_out) {
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ret = -1;
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goto spi_xfer_exit;
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}
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out_buf += fifo_out;
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out_bytes -= fifo_out;
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}
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR) {
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ret = -1;
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goto spi_xfer_exit;
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}
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}
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while (in_bytes > 0) {
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@ -575,28 +637,30 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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dma_in -= fifo_in;
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if (dma_in) {
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tegra_spi_dma_receive(spi, in_buf, dma_in);
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ret = tegra_spi_dma_receive(spi, in_buf, dma_in);
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if (ret != dma_in) {
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ret = -1;
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goto spi_xfer_exit;
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}
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in_buf += dma_in;
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in_bytes -= dma_in;
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}
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if (fifo_in) {
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tegra_spi_fifo_receive(spi, in_buf, fifo_in);
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ret = tegra_spi_fifo_receive(spi, in_buf, fifo_in);
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if (ret != fifo_in) {
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ret = -1;
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goto spi_xfer_exit;
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}
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in_buf += fifo_in;
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in_bytes -= fifo_in;
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}
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR) {
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ret = -1;
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break;
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}
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}
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ret = 0;
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spi_xfer_exit:
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if (ret < 0) {
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dump_spi_regs(spi);
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print_fifo_status(spi);
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if (ret < 0)
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clear_fifo_status(spi);
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}
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return ret;
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}
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