tegra124: Add USB PLL, PHY and EHCI setup code
This patch adds the required bits and pieces to get USB set up correctly for EHCI controllers with UTMI+ PHYs. BUG=None TEST=None Change-Id: I89406ffa25fa96778965f8f1572fad8a74f10844 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174651 Reviewed-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Julius Werner
chrome-internal-fetch
parent
1e44af67cc
commit
ecd5c398ff
7 changed files with 343 additions and 5 deletions
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@ -27,6 +27,7 @@
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#include <soc/nvidia/tegra124/gpio.h>
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#include <soc/nvidia/tegra124/pmc.h>
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#include <soc/nvidia/tegra124/spi.h>
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#include <soc/nvidia/tegra124/usb.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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@ -167,6 +168,11 @@ static void setup_pinmux(void)
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PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
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pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
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PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
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/* TODO: This is supposed to work with the USB special function pinmux,
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* but it doesn't. Go with GPIOs for now and solve the problem later. */
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gpio_output_open_drain(GPIO(N4), 1); /* USB VBUS EN0 */
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gpio_output_open_drain(GPIO(N5), 1); /* USB VBUS EN1 */
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}
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static void setup_kernel_info(void)
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@ -194,16 +200,21 @@ static void setup_ec_spi(void)
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static void mainboard_init(device_t dev)
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{
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setup_pinmux();
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set_clock_sources();
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clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4,
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clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 |
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CLK_L_SDMMC4 | CLK_L_USBD,
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CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
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CLK_H_PMC | CLK_H_MEM,
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CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
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CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
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CLK_V_I2C4,
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CLK_W_DVFS);
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usb_setup_utmip1();
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/* USB2 is the camera, we don't need it in firmware */
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usb_setup_utmip3();
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setup_pinmux();
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i2c_init(0);
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i2c_init(1);
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i2c_init(2);
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120
src/soc/nvidia/tegra/usb.c
Normal file
120
src/soc/nvidia/tegra/usb.c
Normal file
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@ -0,0 +1,120 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/clock.h>
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#include "usb.h"
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/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
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void usb_setup_utmip(struct usb_ctlr *usb)
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{
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/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
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int khz = clock_get_osc_khz();
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/* Stop UTMI+ crystal clock while we mess with its settings */
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clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
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udelay(1);
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/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
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write32(0x8 << 25 | /* HS slew rate [10:4] */
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0x3 << 22 | /* HS driver output 'SETUP' [6:4] */
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0 << 21 | /* LS bias selection */
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0 << 18 | /* PDZI pwrdn */
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0 << 16 | /* PD2 pwrdn */
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0 << 14 | /* PD pwrdn */
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1 << 13 | /* (rst) HS receiver terminations */
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0x1 << 10 | /* (rst) LS falling slew rate */
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0x1 << 8 | /* (rst) LS rising slew rate */
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0x4 << 0 | /* HS driver output 'SETUP' [3:0] */
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0, &usb->utmip.xcvr0);
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write32(0x7 << 18 | /* Termination range adjustment */
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0 << 4 | /* PDDR pwrdn */
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0 << 2 | /* PDCHRP pwrdn */
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0 << 0 | /* PDDISC pwrdn */
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0, &usb->utmip.xcvr1);
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write32(1 << 19 | /* FS send initial J before sync(?) */
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1 << 16 | /* (rst) Allow stuff error on SoP */
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1 << 9 | /* (rst) Check disc only on EoP */
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0, &usb->utmip.tx);
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write32(0x2 << 30 | /* (rst) Keep pattern on active */
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1 << 28 | /* (rst) Realign inertia on pkt */
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0x1 << 24 | /* (rst) edges-1 to move sampling */
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0x3 << 21 | /* (rst) squelch delay on EoP */
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0x11 << 15 | /* cycles until IDLE */
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0x10 << 10 | /* elastic input depth */
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0, &usb->utmip.hsrx0);
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/* U-Boot claims the USBD values for these are used across all UTMI+
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* PHYs. That sounds so horribly wrong that I'm not going to implement
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* it, but keep it in mind if we're ever not using the USBD port. */
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write32(0x1 << 24 | /* HS disconnect detect level [2] */
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1 << 23 | /* (rst) IDPD value */
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1 << 22 | /* (rst) IDPD select */
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1 << 11 | /* (rst) OTG pwrdn */
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0 << 10 | /* bias pwrdn */
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0x1 << 2 | /* HS disconnect detect level [1:0] */
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0x2 << 0 | /* HS squelch detect level */
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0, &usb->utmip.bias0);
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write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */
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1 << 2 | /* (rst) VBUS wakeup pwrdn */
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0 << 0 | /* PDTRK pwrdn */
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0, &usb->utmip.bias1);
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write32(0xffff << 16 | /* (rst) */
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25 * khz / 10 << 0 | /* TODO: what's this, really? */
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0, &usb->utmip.debounce);
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udelay(1);
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setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
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write32(1 << 12 | /* UTMI+ enable */
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0 << 11 | /* UTMI+ reset */
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0, &usb->suspend_ctrl);
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}
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/*
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* Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized
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* after every EHCI reset and before any other actions (such as Run/Stop bit)
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* are taken. We reset the controller here, set those registers and rely on the
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* fact that libpayload doesn't reset EHCI controllers on initialization for
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* whatever weird reason. This is ugly, fragile, and I really don't like it, but
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* making this work will require an ugly hack one way or another so we might as
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* well take the path of least resistance for now.
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*/
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void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
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{
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int timeout = 1000;
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write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
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/* TODO: Resets are long, find way to parallelize... or just use XHCI */
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while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
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/* wait for HC to reset */;
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if (!timeout) {
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printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb);
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return;
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}
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write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */
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write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */
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}
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121
src/soc/nvidia/tegra/usb.h
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121
src/soc/nvidia/tegra/usb.h
Normal file
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@ -0,0 +1,121 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA_USB_H__
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#define __SOC_NVIDIA_TEGRA_USB_H__
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#include <stdint.h>
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struct utmip_ctlr {
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u32 pll0;
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u32 pll1;
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u32 xcvr0;
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u32 bias0;
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u32 hsrx0;
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u32 hsrx1;
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u32 fslsrx0;
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u32 fslsrx1;
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u32 tx;
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u32 misc0;
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u32 misc1;
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u32 debounce;
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u32 batchrgr;
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u32 spare;
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u32 xcvr1;
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u32 bias1;
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u32 bias_sts;
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u32 chrgr_debounce;
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u32 misc_sts;
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u32 pmc_wakeup;
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};
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struct usb_ctlr {
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u32 id;
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u32 _rsv0;
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u32 host;
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u32 device;
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u32 txbuf; /* 0x010 */
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u32 rxbuf;
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u32 _rsv1[58];
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u16 ehci_caplen; /* 0x100 */
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u16 ehci_version;
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u32 ehci_hcsp;
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u32 ehci_hccp;
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u32 _rsv2[5];
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u32 dci_version; /* 0x120 */
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u32 dcc_params;
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u32 extsts;
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u32 extintr;
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u32 ehci_usbcmd; /* 0x130 */
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u32 ehci_usbsts;
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u32 ehci_usbintr;
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u32 ehci_frindex;
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u32 _rsv3; /* 0x140 */
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u32 ehci_periodic_base;
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u32 ehci_async_base;
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u32 async_ttsts;
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u32 burst_size; /* 0x150 */
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u32 tx_fill_tuning;
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u32 _rsv4;
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u32 icusb_ctrl;
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u32 ulpi_viewport; /* 0x160 */
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u32 _rsv5[4];
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u32 ehci_portsc;
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u32 _rsv6[15];
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u32 lpm_ctrl;
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u32 _rsv7[15];
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u32 otgsc;
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u32 usb_mode;
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u32 _rsv8;
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u32 ep_nak; /* 0x200 */
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u32 ep_nak_enable;
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u32 ep_setup;
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u32 ep_init;
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u32 ep_deinit;
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u32 ep_sts;
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u32 ep_complete;
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u32 ep_ctrl[16];
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u32 _rsv9[105];
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u32 suspend_ctrl; /* 0x400 */
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u32 vbus_sensors;
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u32 vbus_wakeup_id;
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u32 alt_vbus_sts;
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u32 legacy_ctrl;
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u32 _rsv10[3];
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u32 interpacket_delay;
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u32 _rsv11[27];
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u32 resume_delay;
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u32 _rsv12;
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u32 spare;
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u32 _rsv13[9];
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u32 new_ctrl;
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u32 _rsv14[207];
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struct utmip_ctlr utmip; /* 0x800 */
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};
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enum usb_phy_type { /* For use in lpm_ctrl[31:29] */
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USB_PHY_UTMIP = 0,
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USB_PHY_ULPI = 2,
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USB_PHY_ICUSB_SER = 3,
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USB_PHY_HSIC = 4,
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};
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void usb_setup_utmip(struct usb_ctlr *usb);
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void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type);
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#endif
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@ -50,6 +50,7 @@ ramstage-y += ../tegra/dp.c
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ramstage-y += ../tegra/gpio.c
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ramstage-y += ../tegra/i2c.c
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ramstage-y += ../tegra/pinmux.c
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ramstage-y += ../tegra/usb.c
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ramstage-y += timer.c
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ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
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@ -18,6 +18,7 @@
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#include <arch/io.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <stdlib.h>
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#include "clk_rst.h"
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#include "cpug.h"
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#include "flow.h"
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@ -205,6 +206,37 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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writel(dividers | PLL_BASE_ENABLE, base);
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}
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static void init_utmip_pll(void)
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{
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int khz = clock_get_osc_khz();
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/* Shut off PLL crystal clock while we mess with it */
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clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
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udelay(1);
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write32(80 << 16 | /* (rst) phy_divn */
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1 << 8 | /* (rst) phy_divm */
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0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
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write32(div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
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0 << 16 | /* PLLU pwrdn */
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0 << 14 | /* pll_enable pwrdn */
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0 << 12 | /* pll_active pwrdn */
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div_round_up(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
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0, &clk_rst->utmip_pll_cfg1);
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/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
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write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
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div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
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div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
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0 << 4 | /* SAMP_C/USB3 pwrdn */
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0 << 2 | /* SAMP_B/XHOST pwrdn */
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0 << 0 | /* SAMP_A/USBD pwrdn */
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0, &clk_rst->utmip_pll_cfg2);
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setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
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}
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/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
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* Will later move it to PLLP in clock_config(). The divisor must be very small
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* to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1
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@ -320,6 +352,7 @@ void clock_init(void)
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init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc);
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init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
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init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
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init_utmip_pll();
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val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
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writel(val, &clk_rst->clk_sys_rate);
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@ -70,7 +70,9 @@ enum {
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TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
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TEGRA_CSITE_BASE = 0x70040000,
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TEGRA_SYSCTR0_BASE = 0x700F0000,
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TEGRA_USB_ADDR_MASK = 0xFFFFC000,
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TEGRA_USBD_BASE = 0x7D000000,
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TEGRA_USB2_BASE = 0x7D004000,
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TEGRA_USB3_BASE = 0x7D008000,
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};
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enum {
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50
src/soc/nvidia/tegra124/usb.h
Normal file
50
src/soc/nvidia/tegra124/usb.h
Normal file
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013, Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
|
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* version 2, as published by the Free Software Foundation.
|
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*
|
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
|
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_NVIDIA_TEGRA124_USB_H_
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#define __SOC_NVIDIA_TEGRA124_USB_H_
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/nvidia/tegra/usb.h>
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static inline void usb_setup_utmip1(void)
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{
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struct usb_ctlr *usb = (void *)TEGRA_USBD_BASE;
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usb_setup_utmip(usb);
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usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
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printk(BIOS_DEBUG, "USBD controller set up with UTMI+ PHY\n");
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}
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|
||||
static inline void usb_setup_utmip2(void)
|
||||
{
|
||||
struct usb_ctlr *usb = (void *)TEGRA_USB2_BASE;
|
||||
usb_setup_utmip(usb);
|
||||
usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
|
||||
printk(BIOS_DEBUG, "USB2 controller set up with UTMI+ PHY\n");
|
||||
}
|
||||
|
||||
static inline void usb_setup_utmip3(void)
|
||||
{
|
||||
struct usb_ctlr *usb = (void *)TEGRA_USB3_BASE;
|
||||
usb_setup_utmip(usb);
|
||||
usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
|
||||
printk(BIOS_DEBUG, "USB3 controller set up with UTMI+ PHY\n");
|
||||
}
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA124_USB_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue