broadwell: Clean up broadwell/systemagent.h
- Remove unused chipset type defines - Remove unused/undefined registers in MCHBAR/DMIBAR/EPBAR - Remove unused function prototypes - Fix MCHBAR macros to use MCH_BASE_ADDRESS - MRC cache defines/prototypes are in soc/intel/common BUG=chrome-os-partner:28234 TEST=None Change-Id: I9477f61d4756f787022245e5c134c0250f20dbe3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198920 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
17353803ba
commit
49d7a023f3
1 changed files with 15 additions and 147 deletions
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@ -18,31 +18,20 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
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#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1
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#ifndef _BROADWELL_SYSTEMAGENT_H_
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#define _BROADWELL_SYSTEMAGENT_H_
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/* Chipset types */
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#define HASWELL_MOBILE 0
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#define HASWELL_DESKTOP 1
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#define HASWELL_SERVER 2
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#include <broadwell/iomap.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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/* Everything below this line is ignored in the DSDT */
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#ifndef __ACPI__
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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/* Device 0:0.0 PCI configuration space */
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#define EPBAR 0x40
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#define MCHBAR 0x48
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#define PCIEXBAR 0x60
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#define DMIBAR 0x68
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define GGC 0x50 /* GMCH Graphics Control */
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#define DEVEN 0x54 /* Device Enable */
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#define DEVEN_D7EN (1 << 14)
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#define DEVEN_D4EN (1 << 7)
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#define DEVEN_D3EN (1 << 5)
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@ -60,7 +49,6 @@
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#define PAM5 0x85
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#define PAM6 0x86
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#define LAC 0x87 /* Legacy Access Control */
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#define SMRAM 0x88 /* System Management RAM Control */
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#define D_OPEN (1 << 6)
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#define D_CLS (1 << 5)
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@ -78,67 +66,25 @@
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#define BGSM 0xb4 /* Base GTT Stolen Memory */
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#define TSEG 0xb8 /* TSEG base */
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#define TOLUD 0xbc /* Top of Low Used Memory */
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#define SKPAD 0xdc /* Scratchpad Data */
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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/* MCHBAR */
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#define BCTRL1 0x3e /* 16bit */
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#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))
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#define MCHBAR_PEI_VERSION 0x5034
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#define BIOS_RESET_CPL 0x5da8
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#define EDRAMBAR 0x5408
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#define MCH_PAIR 0x5418
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#define GDXCBAR 0x5420
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/* Device 0:2.0 PCI configuration space (Graphics Device) */
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#define MSAC 0x62 /* Multi Size Aperture Control */
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#define SWSCI 0xe8 /* SWSCI enable */
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#define ASLS 0xfc /* OpRegion Base */
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/*
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* MCHBAR
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*/
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#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
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#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
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#define BIOS_RESET_CPL 0x5da8 /* 8bit */
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/* Some power MSRs are also represented in MCHBAR */
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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#define MCH_PKG_POWER_LIMIT_HI 0x59a4
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#define MCH_DDR_POWER_LIMIT_LO 0x58e0
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#define MCH_DDR_POWER_LIMIT_HI 0x58e4
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/*
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* EPBAR - Egress Port Root Complex Register Block
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*/
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#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
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#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
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#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
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#define EPPVCCAP1 0x004 /* 32bit */
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#define EPPVCCAP2 0x008 /* 32bit */
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#define EPVC0RCAP 0x010 /* 32bit */
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#define EPVC0RCTL 0x014 /* 32bit */
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#define EPVC0RSTS 0x01a /* 16bit */
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#define EPVC1RCAP 0x01c /* 32bit */
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#define EPVC1RCTL 0x020 /* 32bit */
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#define EPVC1RSTS 0x026 /* 16bit */
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#define EPVC1MTS 0x028 /* 32bit */
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#define EPVC1IST 0x038 /* 64bit */
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#define EPESD 0x044 /* 32bit */
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#define EPLE1D 0x050 /* 32bit */
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#define EPLE1A 0x058 /* 64bit */
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#define EPLE2D 0x060 /* 32bit */
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#define EPLE2A 0x068 /* 64bit */
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#define PORTARB 0x100 /* 256bit */
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/* PCODE MMIO communications live in the MCHBAR. */
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#define BIOS_MAILBOX_INTERFACE 0x5da4
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#define MAILBOX_RUN_BUSY (1 << 31)
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@ -160,82 +106,4 @@
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/*
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* DMIBAR
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*/
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#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
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#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
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#define DMIVCECH 0x000 /* 32bit */
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#define DMIPVCCAP1 0x004 /* 32bit */
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#define DMIPVCCAP2 0x008 /* 32bit */
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#define DMIPVCCCTL 0x00c /* 16bit */
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#define DMIVC0RCAP 0x010 /* 32bit */
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#define DMIVC0RCTL0 0x014 /* 32bit */
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#define DMIVC0RSTS 0x01a /* 16bit */
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#define DMIVC1RCAP 0x01c /* 32bit */
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#define DMIVC1RCTL 0x020 /* 32bit */
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#define DMIVC1RSTS 0x026 /* 16bit */
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#define DMILE1D 0x050 /* 32bit */
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#define DMILE1A 0x058 /* 64bit */
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#define DMILE2D 0x060 /* 32bit */
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#define DMILE2A 0x068 /* 64bit */
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#define DMILCAP 0x084 /* 32bit */
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#define DMILCTL 0x088 /* 16bit */
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#define DMILSTS 0x08a /* 16bit */
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#define DMICTL1 0x0f0 /* 32bit */
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#define DMICTL2 0x0fc /* 32bit */
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#define DMICC 0x208 /* 32bit */
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#define DMIDRCCFG 0xeb4 /* 32bit */
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#ifndef __ASSEMBLER__
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static inline void barrier(void) { asm("" ::: "memory"); }
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#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
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#define PCI_DEVICE_ID_HSW_ULT 0x0a04
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#ifdef __SMM__
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void intel_northbridge_haswell_finalize_smm(void);
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#else /* !__SMM__ */
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void haswell_late_initialization(void);
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void set_translation_table(int start, int end, u64 base, int inc);
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/* debugging functions */
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void print_pci_devices(void);
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void dump_pci_device(unsigned dev);
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void dump_pci_devices(void);
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void dump_spd_registers(void);
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void dump_mem(unsigned start, unsigned end);
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#endif /* !__SMM__ */
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#define MRC_DATA_ALIGN 0x1000
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#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
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struct mrc_data_container {
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u32 mrc_signature; // "MRCD"
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u32 mrc_data_size; // Actual total size of this structure
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u32 mrc_checksum; // IP style checksum
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u32 reserved; // For header alignment
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u8 mrc_data[0]; // Variable size, platform/run time dependent.
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} __attribute__ ((packed));
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struct mrc_data_container *find_current_mrc_cache(void);
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#if !defined(__PRE_RAM__)
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#include "gma.h"
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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#endif
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#endif
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#endif
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#endif
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