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tegra124/nyan*: Obtain DRAM size dynamically

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This eliminates CONFIG_DRAM_SIZE_MB and uses helper functions to
determine DRAM size dynamically. It impacts MMU setup and BCT
selection in romstage, along with framebuffer setup in ramstage.

BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I41e6b24b853b856026fc26f3b1ee8edf2333ad3c
Reviewed-on: https://chromium-review.googlesource.com/184431
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2014-01-29 18:22:17 -08:00 • committed by chrome-internal-fetch
commit a7db717447
10 changed files with 40 additions and 32 deletions
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4
src/mainboard/google/nyan/Kconfig
View file

@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan"
config DRAM_SIZE_MB
int
default 2048
config DRAM_DMA_START
hex
default 0x90000000

19
src/mainboard/google/nyan/romstage.c
View file

@ -26,14 +26,10 @@
#include <cbmem.h>
#include <console/console.h>
#include "soc/nvidia/tegra124/chip.h"
#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h>
#include <timestamp.h>
// Convenient shorthand (in MB)
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
@ -74,6 +70,7 @@ static void configure_l2actlr(void)
static void __attribute__((noinline)) romstage(void)
{
int dram_size_mb;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
@ -84,12 +81,18 @@ static void __attribute__((noinline)) romstage(void)
console_init();
exception_init();
/* used for MMU and CBMEM setup */
dram_size_mb = sdram_size_mb();
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = dram_start + dram_size_mb; /* plus one... */
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start, DCACHE_OFF);
mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

4
src/mainboard/google/nyan_big/Kconfig
View file

@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan Big"
config DRAM_SIZE_MB
int
default 2048
config DRAM_DMA_START
hex
default 0x90000000

19
src/mainboard/google/nyan_big/romstage.c
View file

@ -26,14 +26,10 @@
#include <cbmem.h>
#include <console/console.h>
#include "soc/nvidia/tegra124/chip.h"
#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h>
#include <timestamp.h>
// Convenient shorthand (in MB)
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
@ -74,6 +70,7 @@ static void configure_l2actlr(void)
static void __attribute__((noinline)) romstage(void)
{
int dram_size_mb;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
@ -84,12 +81,18 @@ static void __attribute__((noinline)) romstage(void)
console_init();
exception_init();
/* used for MMU and CBMEM setup */
dram_size_mb = sdram_size_mb();
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = dram_start + dram_size_mb; /* plus one... */
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start, DCACHE_OFF);
mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

3
src/soc/nvidia/tegra/dc.h
View file

@ -569,4 +569,7 @@ struct disp_ctl_win {
void display_startup(device_t dev);
void dp_bringup(u32 winb_addr);
unsigned int fb_base_mb(void);
#endif /* __SOC_NVIDIA_TEGRA_DC_H */

1
src/soc/nvidia/tegra124/Makefile.inc
View file

@ -45,6 +45,7 @@ ramstage-y += dma.c
ramstage-y += i2c.c
ramstage-y += maincpu.S
ramstage-y += monotonic_timer.c
ramstage-y += sdram.c
ramstage-y += soc.c
ramstage-y += sor.c
ramstage-y += spi.c

3
src/soc/nvidia/tegra124/cbmem.c
View file

@ -19,9 +19,10 @@
#include <cbmem.h>
#include <soc/addressmap.h>
#include <soc/nvidia/tegra124/sdram.h>
void *cbmem_top(void)
{
return (void *)(CONFIG_SYS_SDRAM_BASE +
((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL));
((sdram_size_mb() - FB_SIZE_MB)<< 20UL));
}

8
src/soc/nvidia/tegra124/display.c
View file

@ -33,6 +33,7 @@
#include <edid.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/nvidia/tegra124/sdram.h>
#include "chip.h"
#include <soc/display.h>
@ -225,6 +226,11 @@ static void update_window(struct display_controller *dc,
WRITEL(val, &dc->cmd.state_ctrl);
}
uint32_t fb_base_mb(void)
{
return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB);
}
/* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards.
*/
@ -279,7 +285,7 @@ void display_startup(device_t dev)
}
if (! framebuffer_base_mb)
framebuffer_base_mb = FB_BASE_MB;
framebuffer_base_mb = fb_base_mb();
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
config->cache_policy);

5
src/soc/nvidia/tegra124/include/soc/addressmap.h
View file

@ -80,9 +80,6 @@ enum {
TEGRA_I2C_BASE_COUNT = 6,
};
enum {
FB_SIZE_MB = (32),
FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)),
};
#define FB_SIZE_MB (32)
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */

6
src/soc/nvidia/tegra124/soc.c
View file

@ -22,6 +22,7 @@
#include <console/console.h>
#include <device/device.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/nvidia/tegra124/sdram.h>
#include <soc/addressmap.h>
/* this sucks, but for now, fb size/location are hardcoded.
@ -30,10 +31,11 @@
*/
static void soc_enable(device_t dev)
{
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
u32 lcdbase = FB_BASE_MB;
ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
(CONFIG_DRAM_SIZE_MB - fb_size)*KiB);
(sdram_size_mb() - fb_size)*KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
}