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broadwell: Add header for platform PCI devices

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This header will allow the broadwell code to access specific
devices without worrying about the differences in device_t
type between romstage/smm and ram stage.

These new devices will be used in subsequent commits that clean
up the broadwell drivers.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I457c39b6a5262a6ad50034e711de4e8174815d8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 08:35:03 -07:00 • committed by chrome-internal-fetch
commit 6ac4e56db6
2 changed files with 69 additions and 33 deletions
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33
src/soc/intel/broadwell/broadwell/pch.h
View file

@ -21,33 +21,6 @@
#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
#define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
/*
* Lynx Point PCH PCI Devices:
*
* Bus 0:Device 31:Function 0 LPC Controller1
* Bus 0:Device 31:Function 2 SATA Controller #1
* Bus 0:Device 31:Function 3 SMBus Controller
* Bus 0:Device 31:Function 5 SATA Controller #22
* Bus 0:Device 31:Function 6 Thermal Subsystem
* Bus 0:Device 29:Function 03 USB EHCI Controller #1
* Bus 0:Device 26:Function 03 USB EHCI Controller #2
* Bus 0:Device 28:Function 0 PCI Express* Port 1
* Bus 0:Device 28:Function 1 PCI Express Port 2
* Bus 0:Device 28:Function 2 PCI Express Port 3
* Bus 0:Device 28:Function 3 PCI Express Port 4
* Bus 0:Device 28:Function 4 PCI Express Port 5
* Bus 0:Device 28:Function 5 PCI Express Port 6
* Bus 0:Device 28:Function 6 PCI Express Port 7
* Bus 0:Device 28:Function 7 PCI Express Port 8
* Bus 0:Device 27:Function 0 Intel High Definition Audio Controller
* Bus 0:Device 25:Function 0 Gigabit Ethernet Controller
* Bus 0:Device 22:Function 0 Intel Management Engine Interface #1
* Bus 0:Device 22:Function 1 Intel Management Engine Interface #2
* Bus 0:Device 22:Function 2 IDE-R
* Bus 0:Device 22:Function 3 KT
* Bus 0:Device 20:Function 0 xHCI Controller
*/
/* PCH types */
#define PCH_TYPE_LPT 0x8c
#define PCH_TYPE_LPT_LP 0x9c
@ -124,12 +97,6 @@ void pch_enable_lpc(void);
#define PCH_PCS 0x84
#define PCH_PCS_PS_D3HOT 3
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
#define PCH_PCIE_DEV_SLOT 28
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */

69
src/soc/intel/broadwell/broadwell/pci_devs.h Normal file
View file

@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _BROADWELL_PCI_DEVS_H_
#define _BROADWELL_PCI_DEVS_H_
#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
#include <arch/io.h>
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot,func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
#else
#include <device/device.h>
#include <device/pci_def.h>
#define _SA_DEV(slot) dev_find_slot(0, \
PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0))
#define _PCH_DEV(slot,func) dev_find_slot(0, \
PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func))
#endif
/* System Agent Devices */
#define SA_DEV_SLOT_ROOT 0x00
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEV_SLOT_MINIHD 0x03
#define SA_DEV_ROOT _SA_DEV(ROOT)
#define SA_DEV_IGD _SA_DEV(IGD)
#define SA_DEV_MINIHD _SA_DEV(MINIHD)
/* PCH Devices */
#define PCH_DEV_SLOT_XHCI 0x14
#define PCH_DEV_SLOT_SIO 0x15
#define PCH_DEV_SLOT_ME 0x16
#define PCH_DEV_SLOT_HDA 0x1b
#define PCH_DEV_SLOT_PCIE 0x1c
#define PCH_DEV_SLOT_EHCI 0x1d
#define PCH_DEV_SLOT_LPC 0x1f
#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
#define PCH_DEV_UART0 _PCH_DEV(UART0, 0)
#define PCH_DEV_UART1 _PCH_DEV(UART1, 0)
#define PCH_DEV_ME _PCH_DEV(ME, 0)
#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0)
#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
#define PCH_DEV_IDE _PCH_DEV(LPC, 1)
#define PCH_DEV_SATA _PCH_DEV(LPC, 2)
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3)
#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
#endif