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baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI

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The _PRW method needs to specifcy a bit number within
the GPE block to enable wake events associated with a
given device. Therefore, add ACPI_ENABLE_WAKE_SUS_GPIO()
macro for the mainboards' convenience.

BUG=chrome-os-partner:25251
BRANCH=baytrail
TEST=On rambi used macros for touch pad and screen. Noted
     the appropriate bit was enabled for wake. Also was
     able to wake with the track pad.

Change-Id: I98d7c005997bdcaa3646fabec5199fbe013ca52c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2014-01-24 17:10:39 -06:00 • committed by chrome-internal-fetch
commit 78775098a8
1 changed files with 22 additions and 8 deletions
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30
src/soc/intel/baytrail/baytrail/pmc.h
View file

@ -200,14 +200,22 @@
#define CORE_GPIO_EN2 (1 << 26)
#define CORE_GPIO_EN1 (1 << 25)
#define CORE_GPIO_EN0 (1 << 24)
#define SUS_GPIO_EN7 (1 << 23)
#define SUS_GPIO_EN6 (1 << 22)
#define SUS_GPIO_EN5 (1 << 21)
#define SUS_GPIO_EN4 (1 << 20)
#define SUS_GPIO_EN3 (1 << 19)
#define SUS_GPIO_EN2 (1 << 18)
#define SUS_GPIO_EN1 (1 << 17)
#define SUS_GPIO_EN0 (1 << 16)
#define SUS_GPIO_EN7_BIT 23
#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT)
#define SUS_GPIO_EN6_BIT 22
#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT)
#define SUS_GPIO_EN5_BIT 21
#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT)
#define SUS_GPIO_EN4_BIT 20
#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT)
#define SUS_GPIO_EN3_BIT 19
#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT)
#define SUS_GPIO_EN2_BIT 18
#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT)
#define SUS_GPIO_EN1_BIT 17
#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT)
#define SUS_GPIO_EN0_BIT 16
#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT)
#define PME_B0_EN (1 << 13)
#define BATLOW_EN (1 << 10)
#define PCI_EXP_EN (1 << 9)
@ -217,6 +225,8 @@
#define PCIE_WAKE0_EN (1 << 3)
#define SWGPE_EN (1 << 2)
#define HOT_PLUG_EN (1 << 1)
#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT
#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x)
#define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
#define USB_EN (1 << 17) // Legacy USB2 SMI logic
@ -250,6 +260,8 @@
# define RST_CPU (1 << 2)
# define SYS_RST (1 << 1)
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
/* Track power state from reset to log events. */
struct chipset_power_state {
uint16_t pm1_sts;
@ -286,4 +298,6 @@ void southcluster_log_state(void);
static inline void southcluster_log_state(void) {}
#endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _BAYTRAIL_PMC_H_ */