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tegra124: norrin: fix display issue

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Correct norrin display specific settings. Drop venice2 supporting
functions.

norrin display code needs to be clean up.

BUG=None
TEST=built, flash and boot, graphic shown up
BRANCH=None

Change-Id: If62028b6f5cb101c4898f7198c3e057f2bac61f3
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/179745
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Jimmy Zhang 2013-12-11 17:14:48 -08:00 • committed by chrome-internal-fetch
commit c1c1ae69f6
7 changed files with 37 additions and 29 deletions
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2
src/mainboard/google/nyan/devicetree.cb
View file

@ -30,7 +30,7 @@ chip soc/nvidia/tegra124
register "yres" = "768"
# this setting is what nvidia does; it makes no sense
# and does not agree with hardware. Why'd they do it?
register "framebuffer_bits_per_pixel" = "24"
register "framebuffer_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer

5
src/mainboard/google/nyan/mainboard.c
View file

@ -62,10 +62,11 @@ static void set_clock_sources(void)
/* Note source id of PLLP for HOST1x is 4. */
clock_configure_irregular_source(host1x, PLLP, 408000, 4);
/* DISP1 doesn't support a divisor. Use PLLD2_OUT0 which runs at 570MHz. */
/* Use PLLD_OUT0 as clock source for disp1 */
clrsetbits_le32(&clk_rst->clk_src_disp1,
CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
5 /*PLLD2_OUT0 */ << CLK_SOURCE_SHIFT);
2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
}
static void setup_pinmux(void)

2
src/soc/nvidia/tegra124/clk_rst.h
View file

@ -383,8 +383,10 @@ check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT)
/* This bit is different all over the place. Oh joy... */
#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30)
#define PLLC_MISC_LOCK_ENABLE (1 << 24)
#define PLLUD_MISC_LOCK_ENABLE (1 << 22)
#define PLLD_MISC_CLK_ENABLE (1 << 30)
#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18)
#define PLLE_MISC_LOCK_ENABLE (1 << 9)

29
src/soc/nvidia/tegra124/clock.c
View file

@ -96,7 +96,7 @@ struct {
.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
.pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2},
.pllc = {.n = 50, .m = 1, .p = 0},
.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 12, .p = 0, .cpcon = 8}, /* 283 MHz */
.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
.plldp = {.n = 90, .m = 1, .p = 3}, /* 270 MHz */
.plld2 = {.n = 95, .m = 1, .p = 1}, /* 570 MHz */
@ -106,7 +106,7 @@ struct {
.pllx = {.n = 146, .m = 1, .p = 0}, /* 1898 MHz */
.pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8},
.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
.plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 13, .p = 0, .cpcon = 8}, /* 283 MHz*/
.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12},
.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
.plld2 = {.n = 88, .m = 1, .p = 1}, /* 572 MHz */
@ -116,7 +116,7 @@ struct {
.pllx = {.n = 113, .m = 1, .p = 0}, /* 1898.4 MHz */
.pllp = {.n = 170, .m = 7, .p = 0, .cpcon = 4},
.pllc = {.n = 250, .m = 7, .p = 0},
.plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 286, .m = 17, .p = 0, .cpcon = 8}, /* 282.6 MHz*/
.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8},
.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
.plld2 = {.n = 68, .m = 1, .p = 1}, /* 571.2 MHz */
@ -126,7 +126,7 @@ struct {
.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
.pllc = {.n = 125, .m = 4, .p = 0},
.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 251, .m = 17, .p = 0, .cpcon = 8}, /* 283.5 MHz */
.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
.plldp = {.n = 56, .m = 1, .p = 3}, /* 270.75 MHz */
.plld2 = {.n = 59, .m = 1, .p = 1}, /* 570 MHz */
@ -136,7 +136,7 @@ struct {
.pllx = {.n = 73, .m = 1, .p = 0}, /* 1898 MHz */
.pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5},
.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
.plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12},
.plld = {.n = 283, .m = 26, .p = 0, .cpcon = 8}, /* 283 MHz */
.pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8},
.plldp = {.n = 83, .m = 2, .p = 3}, /* 266.50 MHz */
.plld2 = {.n = 88, .m = 2, .p = 1}, /* 570 MHz */
@ -146,7 +146,7 @@ struct {
.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
.pllc = {.n = 125, .m = 4, .p = 0},
.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
.plld = {.n = 125, .m = 17, .p = 0, .cpcon = 8}, /* 282.4 MHz */
.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
.plldp = {.n = 56, .m = 2, .p = 3}, /* 268 MHz */
.plld2 = {.n = 59, .m = 2, .p = 1}, /* 566 MHz */
@ -156,7 +156,7 @@ struct {
.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
.pllp = {.n = 24, .m = 1, .p = 0, .cpcon = 2},
.pllc = {.n = 50, .m = 1, .p = 0},
.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
.plld = {.n = 71, .m = 12, .p = 0, .cpcon = 8}, /* 284 MHz */
.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
.plldp = {.n = 90, .m = 4, .p = 3}, /* 264 MHz */
.plld2 = {.n = 95, .m = 4, .p = 1}, /* 570 MHz */
@ -281,13 +281,15 @@ static void graphics_pll(void)
/* leave dither and undoc bits set, release clamp */
scfg = (1<<28) | (1<<24);
writel(scfg, cfg);
/* set lock bit */
setbits_le32(&clk_rst->plldp_misc, PLLDPD2_MISC_LOCK_ENABLE);
/* a few more undocumented bits. Sorry. */
writel(0x13400000, &clk_rst->plld2_ss_cfg); // undocumented
init_pll(&clk_rst->plld2_base, &clk_rst->plld2_misc, osc_table[osc].plld2);
writel(0x13800000, &clk_rst->plld2_ss_cfg); // undocumented
udelay(10); // wait for plld2 ready
/* init clock source for disp1 */
/* init plld (the actual output is plld_out0 that is 1/2 of plld. */
init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
setbits_le32(&clk_rst->plld_misc, PLLUD_MISC_LOCK_ENABLE);
setbits_le32(&clk_rst->plld_misc, PLLD_MISC_CLK_ENABLE);
udelay(10); /* wait for plld ready */
}
/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
@ -435,7 +437,6 @@ void clock_init(void)
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx);
init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp);
init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
init_utmip_pll();
graphics_pll();

8
src/soc/nvidia/tegra124/display.c
View file

@ -315,7 +315,7 @@ void display_startup(device_t dev)
{ u16 *cp = (void *)(framebuffer_base_mb*MiB);
for(i = 0; i < 1048576*8; i++)
if (i %(2560/2) < 1280/2)
if (i % (1376 / 2) < 688 / 2)
cp[i] = 0x222;
else
cp[i] = 0x888;
@ -324,9 +324,9 @@ void display_startup(device_t dev)
/* tell depthcharge ...
*/
struct edid edid;
edid.x_resolution = 2560;
edid.y_resolution = 1700;
edid.bytes_per_line = 2560 * 2;
edid.x_resolution = 1376;
edid.y_resolution = 768;
edid.bytes_per_line = 1376 * 2;
edid.framebuffer_bits_per_pixel = 16;
set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB));

9
src/soc/nvidia/tegra124/displayhack.c
View file

@ -40,6 +40,7 @@
#include <soc/ardisplay.h>
#include <soc/arsor.h>
#include <soc/ardpaux.h>
//#include <soc/nvidia/tegra/displayport.h>
extern int dump;
unsigned long READL(void *p);
@ -878,11 +879,11 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
// 720x480: 27.00 , 594/22, dp CEA
// 640x480: 23.75 , 475/20, dp VESA
u32 PLL_FREQ = 570;
u32 PLL_FREQ = (12 / 12 * 283) / 1 / 2; /* 141.5 */
u32 PLL_DIV = 2;
u32 SYNC_WIDTH = (10 << 16) | 32;
u32 BACK_PORCH = (36 << 16) | 80;
u32 FRONT_PORCH = (3 << 16) | 48;
u32 SYNC_WIDTH = (8 << 16) | 46;
u32 BACK_PORCH = (6 << 16) | 44;
u32 FRONT_PORCH = (6 << 16) | 44;
u32 HSYNC_NEG = 1;
u32 VSYNC_NEG = 1;

11
src/soc/nvidia/tegra124/dp.c
View file

@ -412,7 +412,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
// jz, changed
// cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
cfg->bits_per_pixel = 24;
cfg->bits_per_pixel = 18;
/* TODO: need to come from the board file */
/* Venice2 settings */
@ -431,7 +431,7 @@ static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
__func__, cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
cfg->lane_count = cfg->max_lane_count;
cfg->link_bw = cfg->max_link_bw;
cfg->link_bw = NV_SOR_LINK_SPEED_G1_62;
cfg->enhanced_framing = cfg->support_enhanced_framing;
return 0;
}
@ -462,6 +462,9 @@ void dp_bringup(u32 winb_addr)
u32 dpcd_rev;
u32 pclk_freq;
u32 xres = 1366; /* norrin display */
u32 yres = 768;
printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
dp->sor.base = (void *)TEGRA_ARM_SOR;
@ -482,7 +485,7 @@ void dp_bringup(u32 winb_addr)
dp_link_training((u32) (dp->link_cfg.lane_count),
(u32) (dp->link_cfg.link_bw));
pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1
pclk_freq = dp_setup_timing(5, xres, yres);
printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n", __func__, pclk_freq);
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
@ -490,7 +493,7 @@ void dp_bringup(u32 winb_addr)
u32 pclkfreq, u32 linkfreq);
dp_misc_setting(dp->link_cfg.bits_per_pixel,
2560, 1700, winb_addr,
xres, yres, winb_addr,
(u32) dp->link_cfg.lane_count,
(u32) dp->link_cfg.enhanced_framing,
(u32) dp->link_cfg.alt_scramber_reset_cap,