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broadwell: Clean up ramstage device and driver operations

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- Add Broadwell/WildcatPoint device IDs
- Remove unsupported Haswell Mobile and LynxPoint-H IDs
- Have all ramstage drivers use broadwell_pci_ops if possible

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I4f3af6e2d6b964ff6b808d09fde3b348bbaf2a3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199180
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 12:34:11 -07:00 • committed by chrome-internal-fetch
commit d8fc9daf12
12 changed files with 151 additions and 250 deletions
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18
src/soc/intel/broadwell/ehci.c
View file

@ -211,20 +211,22 @@ static void usb_ehci_set_resources(struct device *dev)
#endif
}
static struct pci_operations lops_pci = {
static struct pci_operations ehci_ops_pci = {
.set_subsystem = &usb_ehci_set_subsystem,
};
static struct device_operations usb_ehci_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = usb_ehci_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb_ehci_init,
.scan_bus = 0,
.ops_pci = &lops_pci,
.read_resources = &pci_dev_read_resources,
.set_resources = &usb_ehci_set_resources,
.enable_resources = &pci_dev_enable_resources,
.ops_pci = &ehci_ops_pci,
};
static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 };
static const unsigned short pci_device_ids[] = {
0x9c26, /* LynxPoint-LP */
0x9ca6, /* WildcatPoint */
0
};
static const struct pci_driver pch_usb_ehci __pci_driver = {
.ops = &usb_ehci_ops,

40
src/soc/intel/broadwell/hda.c
View file

@ -28,6 +28,7 @@
#include <delay.h>
#include "pch.h"
#include "hda_verb.h"
#include <broadwell/ramstage.h>
const u32 * cim_verb_data = NULL;
u32 cim_verb_data_size = 0;
@ -133,7 +134,7 @@ static void azalia_pch_init(struct device *dev, u32 base)
}
}
static void azalia_init(struct device *dev)
static void hda_init(struct device *dev)
{
u32 base;
struct resource *res;
@ -162,35 +163,22 @@ static void azalia_init(struct device *dev)
}
}
static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations azalia_pci_ops = {
.set_subsystem = azalia_set_subsystem,
static struct device_operations hda_ops = {
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &hda_init,
.ops_pci = &broadwell_pci_ops,
};
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = azalia_init,
.scan_bus = 0,
.ops_pci = &azalia_pci_ops,
static const unsigned short pci_device_ids[] = {
0x9c20, /* LynxPoint-LP */
0x9ca0, /* WildcatPoint */
0
};
static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 };
static const struct pci_driver pch_azalia __pci_driver = {
.ops = &azalia_ops,
static const struct pci_driver pch_hda __pci_driver = {
.ops = &hda_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

27
src/soc/intel/broadwell/igd.c
View file

@ -28,6 +28,7 @@
#include <cpu/intel/haswell/haswell.h>
#include <stdlib.h>
#include <string.h>
#include <broadwell/ramstage.h>
#include "chip.h"
#include "haswell.h"
@ -423,7 +424,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
gtt_write(0x0a188, 0x00000001);
}
static void gma_func0_init(struct device *dev)
static void igd_init(struct device *dev)
{
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
struct northbridge_intel_haswell_config *conf = dev->chip_info;
@ -484,7 +485,7 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
static void gma_read_resources(struct device *dev)
static void igd_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
@ -501,18 +502,12 @@ static void gma_read_resources(struct device *dev)
#endif
}
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
.read_resources = gma_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gma_func0_init,
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
static struct device_operations igd_ops = {
.read_resources = &igd_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &igd_init,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = {
@ -529,8 +524,8 @@ static const unsigned short pci_device_ids[] = {
0,
};
static const struct pci_driver pch_lpc __pci_driver = {
.ops = &gma_func0_ops,
static const struct pci_driver igd_driver __pci_driver = {
.ops = &igd_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

40
src/soc/intel/broadwell/lpc.c
View file

@ -43,6 +43,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
static void pch_enable_apic(struct device *dev)
#include <broadwell/ramstage.h>
{
int i;
u32 reg32;
@ -734,38 +735,13 @@ static void pch_lpc_read_resources(device_t dev)
memset(gnvs, 0, sizeof(global_nvs_t));
}
static void pch_lpc_enable(device_t dev)
{
/* Enable PCH Display Port */
RCBA16(DISPBDF) = 0x0010;
RCBA32_OR(FD2, PCH_ENABLE_DBDF);
pch_enable(dev);
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
static struct device_operations device_ops = {
.read_resources = pch_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_init,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
.read_resources = &pch_lpc_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &lpc_init,
.scan_bus = &scan_static_bus,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = {
@ -789,5 +765,3 @@ static const struct pci_driver pch_lpc __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

29
src/soc/intel/broadwell/me.c
View file

@ -829,21 +829,6 @@ static void intel_me_init(device_t dev)
*/
}
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
static void intel_me_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
@ -856,17 +841,17 @@ static void intel_me_enable(device_t dev)
}
static struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.enable = intel_me_enable,
.init = intel_me_init,
.ops_pci = &pci_ops,
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.enable = &intel_me_enable,
.init = &intel_me_init,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = {
0x8c3a, /* Mobile */
0x9c3a, /* Low Power */
0x9cba, /* WildcatPoint */
0
};

36
src/soc/intel/broadwell/minihd.c
View file

@ -28,6 +28,7 @@
#include <delay.h>
#include <stdlib.h>
#include <southbridge/intel/lynxpoint/hda_verb.h>
#include <broadwell/ramstage.h>
static const u32 minihd_verb_table[] = {
/* coreboot specific header */
@ -106,35 +107,22 @@ static void minihd_init(struct device *dev)
}
}
static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations minihd_pci_ops = {
.set_subsystem = minihd_set_subsystem,
};
static struct device_operations minihd_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = minihd_init,
.scan_bus = 0,
.ops_pci = &minihd_pci_ops,
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &minihd_init,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x0a0c, 0 };
static const unsigned short pci_device_ids[] = {
0x0a0c, /* Haswell */
0x160c, /* Broadwell */
0
};
static const struct pci_driver haswell_minihd __pci_driver = {
static const struct pci_driver minihd_driver __pci_driver = {
.ops = &minihd_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

29
src/soc/intel/broadwell/pcie.c
View file

@ -673,7 +673,7 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x90, ~0, 0);
}
static void pci_init(struct device *dev)
static void pch_pcie_init(struct device *dev)
{
u16 reg16;
u32 reg32;
@ -741,16 +741,13 @@ static void pch_pcie_enable(device_t dev)
static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
pci_write_config32(dev, 0x94,
pci_read_config32(dev, 0));
} else {
pci_write_config32(dev, 0x94,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
if (!vendor || !device)
pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
else
pci_write_config32(dev, 0x94, (device << 16) | vendor);
}
static struct pci_operations pci_ops = {
static struct pci_operations pcie_ops = {
.set_subsystem = pcie_set_subsystem,
};
@ -758,22 +755,22 @@ static struct device_operations device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.init = pch_pcie_init,
.enable = pch_pcie_enable,
.scan_bus = pciexp_scan_bridge,
.ops_pci = &pci_ops,
.ops_pci = &pcie_ops,
};
static const unsigned short pci_device_ids[] = {
/* Lynxpoint Mobile */
0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e,
/* Lynxpoint Low Power */
static const unsigned short pcie_device_ids[] = {
/* Lynxpoint-LP */
0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
/* WildcatPoint */
0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448,
0
};
static const struct pci_driver pch_pcie __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
.devices = pcie_device_ids,
};

35
src/soc/intel/broadwell/sata.c
View file

@ -27,6 +27,7 @@
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
#include <broadwell/ramstage.h>
static inline u32 sir_read(struct device *dev, int idx)
{
@ -326,35 +327,18 @@ static void sata_enable(device_t dev)
pci_write_config16(dev, 0x90, map);
}
static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
};
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.enable = sata_enable,
.scan_bus = 0,
.ops_pci = &sata_pci_ops,
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &sata_init,
.enable = &sata_enable,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = {
0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */
0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */
0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */
0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* LynxPoint-LP */
0x9c83, 0x9c85, 0x282a, 0x9c87, 0x282a, 0x9c8f, /* WildcatPoint */
0
};
@ -363,4 +347,3 @@ static const struct pci_driver pch_sata __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

49
src/soc/intel/broadwell/serialio.c
View file

@ -28,6 +28,7 @@
#include "pch.h"
#include "nvs.h"
#include <broadwell/ramstage.h>
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct device *dev)
{
@ -250,39 +251,37 @@ static void serialio_init(struct device *dev)
}
}
static void serialio_set_subsystem(device_t dev, unsigned vendor,
unsigned device)
static void serialio_set_resources(struct device *dev)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_dev_set_resources(dev);
#if CONFIG_INTEL_PCH_UART_CONSOLE
/* Update UART base address if used for debug */
if (serialio_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res)
uartmem_setbaseaddr(res->base);
}
#endif
}
static struct pci_operations pci_ops = {
.set_subsystem = serialio_set_subsystem,
};
static struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = serialio_init,
.ops_pci = &pci_ops,
.read_resources = &pci_dev_read_resources,
.set_resources = &serialio_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &serialio_init,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = {
0x9c60, /* 0:15.0 - SDMA */
0x9c61, /* 0:15.1 - I2C0 */
0x9c62, /* 0:15.2 - I2C1 */
0x9c65, /* 0:15.3 - SPI0 */
0x9c66, /* 0:15.4 - SPI1 */
0x9c63, /* 0:15.5 - UART0 */
0x9c64, /* 0:15.6 - UART1 */
0x9c35, /* 0:17.0 - SDIO */
0x9c60, 0x9ce0, /* 0:15.0 - SDMA */
0x9c61, 0x9ce1, /* 0:15.1 - I2C0 */
0x9c62, 0x9ce2, /* 0:15.2 - I2C1 */
0x9c65, 0x9ce5, /* 0:15.3 - SPI0 */
0x9c66, 0x9ce6, /* 0:15.4 - SPI1 */
0x9c63, 0x9ce3, /* 0:15.5 - UART0 */
0x9c64, 0x9ce4, /* 0:15.6 - UART1 */
0x9c35, 0x9cb5, /* 0:17.0 - SDIO */
0
};

34
src/soc/intel/broadwell/smbus.c
View file

@ -28,6 +28,7 @@
#include <arch/io.h>
#include "pch.h"
#include "smbus.h"
#include <broadwell/ramstage.h>
static void pch_smbus_init(device_t dev)
{
@ -75,21 +76,6 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations smbus_pci_ops = {
.set_subsystem = smbus_set_subsystem,
};
static void smbus_read_resources(device_t dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
@ -104,16 +90,20 @@ static void smbus_read_resources(device_t dev)
}
static struct device_operations smbus_ops = {
.read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.scan_bus = scan_static_bus,
.init = pch_smbus_init,
.read_resources = &smbus_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.scan_bus = &scan_static_bus,
.init = &pch_smbus_init,
.ops_smbus_bus = &lops_smbus_bus,
.ops_pci = &smbus_pci_ops,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x9c22, 0 };
static const unsigned short pci_device_ids[] = {
0x9c22, /* LynxPoint */
0x9ca2, /* WildcatPoint */
0
};
static const struct pci_driver pch_smbus __pci_driver = {
.ops = &smbus_ops,

46
src/soc/intel/broadwell/systemagent.c
View file

@ -38,6 +38,7 @@
#include <romstage_handoff.h>
#include "chip.h"
#include "haswell.h"
#include <broadwell/ramstage.h>
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
@ -381,7 +382,7 @@ static void mc_add_dram_resources(device_t dev)
#endif
}
static void mc_read_resources(device_t dev)
static void systemagent_read_resources(device_t dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);
@ -393,18 +394,7 @@ static void mc_read_resources(device_t dev)
mc_add_dram_resources(dev);
}
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static void northbridge_init(struct device *dev)
static void systemagent_init(struct device *dev)
{
u8 bios_reset_cpl, pair;
@ -441,7 +431,7 @@ void *cbmem_top(void)
return (void *)(reg & ~((1 << 20) - 1));
}
static void northbridge_enable(device_t dev)
static void systemagent_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
struct romstage_handoff *handoff;
@ -461,17 +451,25 @@ static void northbridge_enable(device_t dev)
#endif
}
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
static struct device_operations systemagent_ops = {
.read_resources = &systemagent_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &systemagent_init,
.enable = &systemagent_enable,
.ops_pci = &broadwell_pci_ops,
};
static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = northbridge_enable,
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
static const unsigned short systemagent_ids[] = {
0x0a04, /* Haswell ULT */
0x1604, /* Broadwell-U/Y */
0x1610, /* Broadwell-H Desktop */
0x1614, /* Broadwell-H Mobile */
0
};
static const struct pci_driver systemagent_driver __pci_driver = {
.ops = &systemagent_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = systemagent_ids
};

18
src/soc/intel/broadwell/xhci.c
View file

@ -26,6 +26,7 @@
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
#include <broadwell/ramstage.h>
static u32 usb_xhci_mem_base(device_t dev)
{
@ -383,16 +384,17 @@ static struct pci_operations lops_pci = {
};
static struct device_operations usb_xhci_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = usb_xhci_init,
.ops_pci = &lops_pci,
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.ops_pci = &broadwell_pci_ops,
};
static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */
0x9c31, /* LynxPoint-LP */
0 };
static const unsigned short pci_device_ids[] = {
0x9c31, /* LynxPoint-LP */
0x9cb1, /* WildcatPoint */
0
};
static const struct pci_driver pch_usb_xhci __pci_driver = {
.ops = &usb_xhci_ops,