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broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c

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Add a new file to contain the functions for finding the top of usable
memory.  This is used in romstage (after raminit) and in ramstage.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I71cc010b4419c7b54820df04b5a80b2ad955905f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 13:48:24 -07:00 • committed by chrome-internal-fetch
commit 68955ba4ff
3 changed files with 39 additions and 25 deletions
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39
src/soc/intel/broadwell/memmap.c Normal file
View file

@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
#include <broadwell/pci_devs.h>
#include <broadwell/systemagent.h>
static unsigned long get_top_of_ram(void)
{
/*
* Base of TSEG is top of usable DRAM below 4GiB. The register has
* 1 MiB alignement.
*/
u32 tom = pci_read_config32(SA_DEV_ROOT, TSEG);
return (unsigned long) tom & ~((1 << 20) - 1);
}
void *cbmem_top(void)
{
return (void *)get_top_of_ram();
}

15
src/soc/intel/broadwell/romstage/raminit.c
View file

@ -161,18 +161,3 @@ void sdram_initialize(struct pei_data *pei_data)
report_memory_config();
}
void *cbmem_top(void)
{
/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
return (void *)get_top_of_ram();
}
unsigned long get_top_of_ram(void)
{
/*
* Base of TSEG is top of usable DRAM below 4GiB. The register has
* 1 MiB alignement.
*/
u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
return (unsigned long) tom & ~((1 << 20) - 1);
}

10
src/soc/intel/broadwell/systemagent.c
View file

@ -421,16 +421,6 @@ static void systemagent_init(struct device *dev)
MCHBAR32(0x5500) = 0x00100001;
}
void *cbmem_top(void)
{
u32 reg;
/* The top the reserve regions fall just below the TSEG region. */
reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
return (void *)(reg & ~((1 << 20) - 1));
}
static void systemagent_enable(device_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME