broadwell: pch.h: split RCBA into new header
Split out defines for RCBA related registers/bits into a separate header file in broadwell/rcba.h. BUG=chrome-os-partner:28234 TEST=None Change-Id: I070317015b546bb8a641e9a12279e3f86152ca66 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198428 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
97a8d0b051
commit
fa217361b2
2 changed files with 166 additions and 229 deletions
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@ -95,46 +95,6 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
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void usb_xhci_route_all(void);
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#endif
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/* State Machine configuration. */
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#define RCBA_REG_SIZE_MASK 0x8000
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#define RCBA_REG_SIZE_16 0x8000
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#define RCBA_REG_SIZE_32 0x0000
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#define RCBA_COMMAND_MASK 0x000f
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#define RCBA_COMMAND_SET 0x0001
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#define RCBA_COMMAND_READ 0x0002
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#define RCBA_COMMAND_RMW 0x0003
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#define RCBA_COMMAND_END 0x0007
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#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \
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{ .command = command_, \
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.reg = reg_, \
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.mask = mask_, \
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.or_value = or_value_ \
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}
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#define RCBA_SET_REG_32(reg_, value_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_SET, reg_, 0, value_)
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#define RCBA_READ_REG_32(reg_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_READ, reg_, 0, 0)
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#define RCBA_RMW_REG_32(reg_, mask_, or_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_RMW, reg_, mask_, or_)
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#define RCBA_SET_REG_16(reg_, value_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_SET, reg_, 0, value_)
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#define RCBA_READ_REG_16(reg_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_READ, reg_, 0, 0)
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#define RCBA_RMW_REG_16(reg_, mask_, or_) \
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RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_RMW, reg_, mask_, or_)
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#define RCBA_END_CONFIG \
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RCBA_ENCODE_COMMAND(RCBA_COMMAND_END, 0, 0, 0)
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struct rcba_config_instruction
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{
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u16 command;
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u16 reg;
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u32 mask;
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u32 or_value;
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};
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#if !defined(__ASSEMBLER__)
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void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
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int pch_silicon_revision(void);
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@ -478,195 +438,6 @@ void pch_enable_lpc(void);
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#define PMBASE 0x40
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/* Root Complex Register Block */
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#define RCBA 0xf0
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#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
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#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
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#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
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#define RCBA_AND_OR(bits, x, and, or) \
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RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
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#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
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#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
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#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
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#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
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#define VCH 0x0000 /* 32bit */
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#define VCAP1 0x0004 /* 32bit */
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#define VCAP2 0x0008 /* 32bit */
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#define PVC 0x000c /* 16bit */
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#define PVS 0x000e /* 16bit */
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#define V0CAP 0x0010 /* 32bit */
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#define V0CTL 0x0014 /* 32bit */
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#define V0STS 0x001a /* 16bit */
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#define V1CAP 0x001c /* 32bit */
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#define V1CTL 0x0020 /* 32bit */
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#define V1STS 0x0026 /* 16bit */
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#define RCTCL 0x0100 /* 32bit */
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#define ESD 0x0104 /* 32bit */
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#define ULD 0x0110 /* 32bit */
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#define ULBA 0x0118 /* 64bit */
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#define RP1D 0x0120 /* 32bit */
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#define RP1BA 0x0128 /* 64bit */
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#define RP2D 0x0130 /* 32bit */
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#define RP2BA 0x0138 /* 64bit */
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#define RP3D 0x0140 /* 32bit */
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#define RP3BA 0x0148 /* 64bit */
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#define RP4D 0x0150 /* 32bit */
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#define RP4BA 0x0158 /* 64bit */
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#define HDD 0x0160 /* 32bit */
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#define HDBA 0x0168 /* 64bit */
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#define RP5D 0x0170 /* 32bit */
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#define RP5BA 0x0178 /* 64bit */
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#define RP6D 0x0180 /* 32bit */
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#define RP6BA 0x0188 /* 64bit */
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#define RPC 0x0400 /* 32bit */
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#define RPFN 0x0404 /* 32bit */
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/* Root Port configuratinon space hide */
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#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
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/* Get the function number assigned to a Root Port */
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#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
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/* Set the function number for a Root Port */
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#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
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/* Root Port function number mask */
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#define RPFN_FNMASK(port) (7 << ((port) * 4))
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#define TRSR 0x1e00 /* 8bit */
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#define TRCR 0x1e10 /* 64bit */
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#define TWDR 0x1e18 /* 64bit */
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#define IOTR0 0x1e80 /* 64bit */
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#define IOTR1 0x1e88 /* 64bit */
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#define IOTR2 0x1e90 /* 64bit */
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#define IOTR3 0x1e98 /* 64bit */
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#define TCTL 0x3000 /* 8bit */
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#define NOINT 0
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#define INTA 1
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#define INTB 2
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#define INTC 3
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#define INTD 4
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#define DIR_IDR 12 /* Interrupt D Pin Offset */
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#define DIR_ICR 8 /* Interrupt C Pin Offset */
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#define DIR_IBR 4 /* Interrupt B Pin Offset */
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#define DIR_IAR 0 /* Interrupt A Pin Offset */
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#define PIRQA 0
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#define PIRQB 1
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#define PIRQC 2
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#define PIRQD 3
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#define PIRQE 4
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#define PIRQF 5
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#define PIRQG 6
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#define PIRQH 7
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_READY 0x0001
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#define IOBPS_TX_MASK 0x0006
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#define IOBPS_MASK 0xff00
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#define IOBPS_READ 0x0600
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#define IOBPS_WRITE 0x0700
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#define IOBPU 0x233a
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#define IOBPU_MAGIC 0xf000
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#define D31IP 0x3100 /* 32bit */
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#define D31IP_TTIP 24 /* Thermal Throttle Pin */
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#define D31IP_SIP2 20 /* SATA Pin 2 */
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#define D31IP_SMIP 12 /* SMBUS Pin */
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#define D31IP_SIP 8 /* SATA Pin */
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#define D30IP 0x3104 /* 32bit */
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#define D30IP_PIP 0 /* PCI Bridge Pin */
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#define D29IP 0x3108 /* 32bit */
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#define D29IP_E1P 0 /* EHCI #1 Pin */
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#define D28IP 0x310c /* 32bit */
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#define D28IP_P8IP 28 /* PCI Express Port 8 */
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#define D28IP_P7IP 24 /* PCI Express Port 7 */
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#define D28IP_P6IP 20 /* PCI Express Port 6 */
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#define D28IP_P5IP 16 /* PCI Express Port 5 */
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#define D28IP_P4IP 12 /* PCI Express Port 4 */
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#define D28IP_P3IP 8 /* PCI Express Port 3 */
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#define D28IP_P2IP 4 /* PCI Express Port 2 */
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#define D28IP_P1IP 0 /* PCI Express Port 1 */
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#define D27IP 0x3110 /* 32bit */
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#define D27IP_ZIP 0 /* HD Audio Pin */
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#define D26IP 0x3114 /* 32bit */
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#define D26IP_E2P 0 /* EHCI #2 Pin */
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#define D25IP 0x3118 /* 32bit */
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#define D25IP_LIP 0 /* GbE LAN Pin */
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#define D22IP 0x3124 /* 32bit */
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#define D22IP_KTIP 12 /* KT Pin */
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#define D22IP_IDERIP 8 /* IDE-R Pin */
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#define D22IP_MEI2IP 4 /* MEI #2 Pin */
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#define D22IP_MEI1IP 0 /* MEI #1 Pin */
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#define D20IP 0x3128 /* 32bit */
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#define D20IP_XHCI 0 /* XHCI Pin */
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit */
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#define D29IR 0x3144 /* 16bit */
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#define D28IR 0x3146 /* 16bit */
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define D23IR 0x3158 /* 16bit */
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#define D22IR 0x315c /* 16bit */
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#define D20IR 0x3160 /* 16bit */
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#define D21IR 0x3164 /* 16bit */
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#define D19IR 0x3168 /* 16bit */
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#define ACPIIRQEN 0x31e0 /* 32bit */
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#define OIC 0x31fe /* 16bit */
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#define PMSYNC_CONFIG 0x33c4 /* 32bit */
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#define PMSYNC_CONFIG2 0x33cc /* 32bit */
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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#define DIR_ROUTE(a,b,c,d) \
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(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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#define RC 0x3400 /* 32bit */
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#define HPTC 0x3404 /* 32bit */
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#define GCS 0x3410 /* 32bit */
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#define BUC 0x3414 /* 32bit */
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#define PCH_DISABLE_GBE (1 << 5)
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#define FD 0x3418 /* 32bit */
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#define DISPBDF 0x3424 /* 16bit */
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#define FD2 0x3428 /* 32bit */
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#define CG 0x341c /* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS (1 << 0)
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#define PCH_DISABLE_ADSPD (1 << 1)
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#define PCH_DISABLE_SATA1 (1 << 2)
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#define PCH_DISABLE_SMBUS (1 << 3)
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#define PCH_DISABLE_HD_AUDIO (1 << 4)
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#define PCH_DISABLE_EHCI2 (1 << 13)
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#define PCH_DISABLE_LPC (1 << 14)
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#define PCH_DISABLE_EHCI1 (1 << 15)
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#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
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#define PCH_DISABLE_THERMAL (1 << 24)
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#define PCH_DISABLE_SATA2 (1 << 25)
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#define PCH_DISABLE_XHCI (1 << 27)
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/* Function Disable 2 RCBA 0x3428 */
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#define PCH_DISABLE_KT (1 << 4)
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#define PCH_DISABLE_IDER (1 << 3)
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#define PCH_DISABLE_MEI2 (1 << 2)
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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* should support most common flash chips.
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166
src/soc/intel/broadwell/broadwell/rcba.h
Normal file
166
src/soc/intel/broadwell/broadwell/rcba.h
Normal file
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@ -0,0 +1,166 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_RCBA_H_
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#define _BROADWELL_RCBA_H_
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#include <broadwell/iomap.h>
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#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x))
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#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x))
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#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x))
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#define RCBA_AND_OR(bits, x, and, or) \
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RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
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#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
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#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
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#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
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#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
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#define RPC 0x0400 /* 32bit */
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#define RPFN 0x0404 /* 32bit */
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/* Root Port configuratinon space hide */
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#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
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/* Get the function number assigned to a Root Port */
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#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
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/* Set the function number for a Root Port */
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#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
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/* Root Port function number mask */
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#define RPFN_FNMASK(port) (7 << ((port) * 4))
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#define NOINT 0
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#define INTA 1
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#define INTB 2
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#define INTC 3
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#define INTD 4
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#define DIR_IDR 12 /* Interrupt D Pin Offset */
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#define DIR_ICR 8 /* Interrupt C Pin Offset */
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#define DIR_IBR 4 /* Interrupt B Pin Offset */
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#define DIR_IAR 0 /* Interrupt A Pin Offset */
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#define PIRQA 0
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#define PIRQB 1
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#define PIRQC 2
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#define PIRQD 3
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#define PIRQE 4
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#define PIRQF 5
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#define PIRQG 6
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#define PIRQH 7
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_READY 0x0001
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#define IOBPS_TX_MASK 0x0006
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#define IOBPS_MASK 0xff00
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#define IOBPS_READ 0x0600
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#define IOBPS_WRITE 0x0700
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#define IOBPU 0x233a
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#define IOBPU_MAGIC 0xf000
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#define D31IP 0x3100 /* 32bit */
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#define D31IP_TTIP 24 /* Thermal Throttle Pin */
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#define D31IP_SIP2 20 /* SATA Pin 2 */
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#define D31IP_SMIP 12 /* SMBUS Pin */
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#define D31IP_SIP 8 /* SATA Pin */
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#define D30IP 0x3104 /* 32bit */
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#define D30IP_PIP 0 /* PCI Bridge Pin */
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#define D29IP 0x3108 /* 32bit */
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#define D29IP_E1P 0 /* EHCI #1 Pin */
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#define D28IP 0x310c /* 32bit */
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#define D28IP_P8IP 28 /* PCI Express Port 8 */
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#define D28IP_P7IP 24 /* PCI Express Port 7 */
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#define D28IP_P6IP 20 /* PCI Express Port 6 */
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#define D28IP_P5IP 16 /* PCI Express Port 5 */
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#define D28IP_P4IP 12 /* PCI Express Port 4 */
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#define D28IP_P3IP 8 /* PCI Express Port 3 */
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#define D28IP_P2IP 4 /* PCI Express Port 2 */
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#define D28IP_P1IP 0 /* PCI Express Port 1 */
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#define D27IP 0x3110 /* 32bit */
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#define D27IP_ZIP 0 /* HD Audio Pin */
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#define D26IP 0x3114 /* 32bit */
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#define D26IP_E2P 0 /* EHCI #2 Pin */
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#define D25IP 0x3118 /* 32bit */
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#define D25IP_LIP 0 /* GbE LAN Pin */
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#define D22IP 0x3124 /* 32bit */
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#define D22IP_KTIP 12 /* KT Pin */
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#define D22IP_IDERIP 8 /* IDE-R Pin */
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#define D22IP_MEI2IP 4 /* MEI #2 Pin */
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#define D22IP_MEI1IP 0 /* MEI #1 Pin */
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#define D20IP 0x3128 /* 32bit */
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#define D20IP_XHCI 0 /* XHCI Pin */
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit */
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#define D29IR 0x3144 /* 16bit */
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#define D28IR 0x3146 /* 16bit */
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define D23IR 0x3158 /* 16bit */
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#define D22IR 0x315c /* 16bit */
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#define D20IR 0x3160 /* 16bit */
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#define D21IR 0x3164 /* 16bit */
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#define D19IR 0x3168 /* 16bit */
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#define ACPIIRQEN 0x31e0 /* 32bit */
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#define OIC 0x31fe /* 16bit */
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#define PMSYNC_CONFIG 0x33c4 /* 32bit */
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#define PMSYNC_CONFIG2 0x33cc /* 32bit */
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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#define DIR_ROUTE(a,b,c,d) \
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(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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#define RC 0x3400 /* 32bit */
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#define HPTC 0x3404 /* 32bit */
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#define GCS 0x3410 /* 32bit */
|
||||
#define BUC 0x3414 /* 32bit */
|
||||
#define PCH_DISABLE_GBE (1 << 5)
|
||||
#define FD 0x3418 /* 32bit */
|
||||
#define FDSW 0x3420 /* 8bit */
|
||||
#define DISPBDF 0x3424 /* 16bit */
|
||||
#define FD2 0x3428 /* 32bit */
|
||||
#define CG 0x341c /* 32bit */
|
||||
|
||||
/* Function Disable 1 RCBA 0x3418 */
|
||||
#define PCH_DISABLE_ALWAYS (1 << 0)
|
||||
#define PCH_DISABLE_ADSPD (1 << 1)
|
||||
#define PCH_DISABLE_SATA1 (1 << 2)
|
||||
#define PCH_DISABLE_SMBUS (1 << 3)
|
||||
#define PCH_DISABLE_HD_AUDIO (1 << 4)
|
||||
#define PCH_DISABLE_EHCI2 (1 << 13)
|
||||
#define PCH_DISABLE_LPC (1 << 14)
|
||||
#define PCH_DISABLE_EHCI1 (1 << 15)
|
||||
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
|
||||
#define PCH_DISABLE_THERMAL (1 << 24)
|
||||
#define PCH_DISABLE_SATA2 (1 << 25)
|
||||
#define PCH_DISABLE_XHCI (1 << 27)
|
||||
|
||||
/* Function Disable 2 RCBA 0x3428 */
|
||||
#define PCH_DISABLE_KT (1 << 4)
|
||||
#define PCH_DISABLE_IDER (1 << 3)
|
||||
#define PCH_DISABLE_MEI2 (1 << 2)
|
||||
#define PCH_DISABLE_MEI1 (1 << 1)
|
||||
#define PCH_ENABLE_DBDF (1 << 0)
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue