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tegra124: use pll_c_out1 as sclk parent

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The kernel does not support using pll_c_out0 as the parent of sclk,
nor does it support the use of super dividers.  The reason for this
is that DVFS schemes must use the pre-divided rate with using super
dividers when setting voltages, which makes them essentially useless.
Instead, set pll_c_out1 to 300Mhz (pll_c / 2) and use that as the parent
of sclk.

BUG=chrome-os-partner:24487
TEST=Kernel now boots with sclk DVFS enabled
BRANCH=None

Change-Id: Ia106963d290122cddbaf9eaf88047fda2dfe8b8a
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180865
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
This commit is contained in:
Andrew Bresticker 2013-12-18 22:35:16 -08:00 • committed by chrome-internal-fetch
commit 418337a5bd
1 changed files with 3 additions and 4 deletions
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7
src/soc/nvidia/tegra124/clock.c
View file

@ -401,11 +401,10 @@ void clock_init(void)
* features section in the TRM). */
write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */
write32(0 << SCLK_DIVIDEND_SHIFT |
(div_round_up(TEGRA_PLLC_KHZ, 300000) - 1) << SCLK_DIVISOR_SHIFT
| SCLK_DIV_ENB, &clk_rst->super_sclk_div);
write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out);
write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
SCLK_SOURCE_PLLC_OUT0 << SCLK_RUN_SHIFT,
SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
&clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */