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tegra124: Never touch MEM(MC)/EMC clocks in ramstage.

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The clocks for MEM(MC)/EMC should be either initialized by BootROM, or in the
step of SDRAM initialization. Changing their states in ramstage may cause
unexpected results (note MC even always ignores RESET states).

To make it clear, we should remove MEM/EMC from the clock initialization list.

BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully.

Change-Id: Icff9f78810ed5bd693b48d7b6d436ce2db919a5e
Reviewed-on: https://chromium-review.googlesource.com/183623
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Hung-Te Lin 2014-01-23 18:58:41 +08:00 • committed by chrome-internal-fetch
commit 8e3bb34d4a
1 changed files with 5 additions and 2 deletions
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7
src/mainboard/google/nyan/mainboard.c
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@ -243,14 +243,17 @@ static void mainboard_init(device_t dev)
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*
* Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either
* initialized by BootROM, or in romstage SDRAM initialization.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC |
CLK_H_USB3,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,