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tegra124: Set Tx FIFO threshold value to recommended setting

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This is essentially a direct port of CL:174505. It sets the EHCI
controllers Tx FIFO threshold setting to the recommended value for HOST
mode, which seems to help prevent FIFO underruns between the memory/AHB
and the host controller. This is necessary to get larger OUT transfers
to work, but there are still a few more general clock changes
concerning other AHB problems needed before they will really be usable.

BUG=None
TEST=None

Change-Id: I12783ba0a986678715d42e3d798756fa3d1ad690
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175200
Reviewed-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Julius Werner 2013-10-25 17:49:26 -07:00 • committed by chrome-internal-fetch
commit c8f086711c
1 changed files with 8 additions and 7 deletions
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15
src/soc/nvidia/tegra/usb.c
View file

@ -93,13 +93,13 @@ void usb_setup_utmip(struct usb_ctlr *usb)
}
/*
* Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized
* after every EHCI reset and before any other actions (such as Run/Stop bit)
* are taken. We reset the controller here, set those registers and rely on the
* fact that libpayload doesn't reset EHCI controllers on initialization for
* whatever weird reason. This is ugly, fragile, and I really don't like it, but
* making this work will require an ugly hack one way or another so we might as
* well take the path of least resistance for now.
* Tegra EHCI controllers need their usb_mode, lpm_ctrl and tx_fill_tuning
* registers initialized after every EHCI reset and before any other actions
* (such as Run/Stop bit) are taken. We reset the controller here, set those
* registers and rely on the fact that libpayload doesn't reset EHCI controllers
* on initialization for whatever weird reason. This is ugly, fragile, and I
* really don't like it, but making this work will require an ugly hack one way
* or another so we might as well take the path of least resistance for now.
*/
void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
{
@ -117,4 +117,5 @@ void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */
write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */
write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */
}