broadwell: romstage: Convert pch init to reg_script
- Convert the pch early chipset init code to reg_script format. - Remove the generic romstage code from pch_early_init() as this is now done in romstage_main(). - Use base addresses from broadwell/iomap.h - Start the HPET counter after enabling it as it is needed by the memory training reference code. - Set PCH interrupt routing here instead of in mainboard code. BUG=chrome-os-partner:28234 TEST=None Change-Id: I66a8b54ec81d5126cf4d59196e0e06ea949286d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199365 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
c2ea2d3a0c
commit
4383de5846
1 changed files with 102 additions and 118 deletions
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@ -17,146 +17,130 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <elog.h>
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#include "pch.h"
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#include "chip.h"
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#include <reg_script.h>
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#include <broadwell/iomap.h>
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#include <broadwell/lpc.h>
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#include <broadwell/pch.h>
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#include <broadwell/pci_devs.h>
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#include <broadwell/pm.h>
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#include <broadwell/rcba.h>
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#include <broadwell/romstage.h>
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#include <broadwell/smbus.h>
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#include <chip.h>
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#if CONFIG_INTEL_LYNXPOINT_LP
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#include "lp_gpio.h"
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#else
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#include "gpio.h"
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#endif
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#include <vendorcode/google/chromeos/chromeos.h>
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const struct rcba_config_instruction pch_early_config[] = {
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/* Enable IOAPIC */
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RCBA_SET_REG_16(OIC, 0x0100),
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/* PCH BWG says to read back the IOAPIC enable register */
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RCBA_READ_REG_16(OIC),
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RCBA_END_CONFIG,
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};
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int pch_is_lp(void)
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{
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u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
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return id == PCH_TYPE_LPT_LP;
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}
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static void pch_enable_bars(void)
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{
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/* Setting up Southbridge. In the northbridge code. */
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pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1);
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pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
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/* Enable ACPI BAR */
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pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
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pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
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/* Enable GPIO functionality. */
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pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
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}
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static void pch_generic_setup(void)
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{
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printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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printk(BIOS_DEBUG, " done.\n");
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}
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static int sleep_type_s3(void)
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{
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u32 pm1_cnt;
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u16 pm1_sts;
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int is_s3 = 0;
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
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if (pm1_sts & WAK_STS) {
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
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if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) {
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/* Clear SLP_TYPE. */
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outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
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is_s3 = 1;
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}
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}
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return is_s3;
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}
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void pch_enable_lpc(void)
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{
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const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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const struct southbridge_intel_lynxpoint_config *config = NULL;
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const struct reg_script pch_early_init_script[] = {
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/* Setup southbridge BARs */
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REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
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REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
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REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
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REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
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REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
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/* Set COM1/COM2 decode range */
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
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REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
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/* Enable legacy decode ranges */
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REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
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COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
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/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */
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u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
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COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
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pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
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/* Enable IOAPIC */
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REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
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/* Read back for posted write */
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REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
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/* Set up generic decode ranges */
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if (!dev)
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return;
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if (dev->chip_info)
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config = dev->chip_info;
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if (!config)
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/* Set HPET address and enable it */
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REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
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/* Read back for posted write */
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REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
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/* Enable HPET to start counter */
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REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
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/* Disable reset */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
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/* TCO timer halt */
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REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
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/* Enable upper 128 bytes of CMOS */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
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/* Disable unused device (always) */
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REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
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REG_SCRIPT_END
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};
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const struct reg_script pch_interrupt_init_script[] = {
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P1IP PCIE INTA -> PIRQA
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* D29IP_E1P EHCI INTA -> PIRQD
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* D20IP_XHCI XHCI INTA -> PIRQC (MSI)
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQA
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*/
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/* Device interrupt pin register (board specific) */
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP,
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(INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP,
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(INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P4IP)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)),
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/* Device interrupt route registers */
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */
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DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */
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DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */
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DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */
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DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */
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DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */
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DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */
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DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),
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REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */
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DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),
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REG_SCRIPT_END
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};
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static void pch_enable_lpc(void)
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{
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/* Lookup device tree in romstage */
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const struct device *dev;
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const config_t *config;
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dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
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pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
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}
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int early_pch_init(const void *gpio_map,
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const struct rcba_config_instruction *rcba_config)
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void pch_early_init(void)
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{
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int wake_from_s3;
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reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
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reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
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pch_enable_lpc();
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pch_enable_bars();
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#if CONFIG_INTEL_LYNXPOINT_LP
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setup_pch_lp_gpios(gpio_map);
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#else
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setup_pch_gpios(gpio_map);
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#endif
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#if CONFIG_CHROMEOS
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save_chromeos_gpios();
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#endif
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console_init();
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pch_generic_setup();
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/* Enable SMBus for reading SPDs. */
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enable_smbus();
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/* Early PCH RCBA settings */
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pch_config_rcba(pch_early_config);
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/* Mainboard RCBA settings */
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pch_config_rcba(rcba_config);
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wake_from_s3 = sleep_type_s3();
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#if CONFIG_ELOG_BOOT_COUNT
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if (!wake_from_s3)
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boot_count_increment();
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#endif
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/* Report if we are waking from s3. */
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return wake_from_s3;
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}
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