nyan_big: Initialize SDRAM without BootROM.
To support arbitrary numbers of memory configuration, we are now ready to remove SDRAM configurations from BCT and do SDRAM initialization in ROM stage. BUG=none TEST=emerge-nyan_big chromeos-coreboot-nyan # Built successfully. BRANCH=nyan_big Change-Id: Id8673b9ec8c59e450d195758492d8e3484e02edc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183624
This commit is contained in:
Hung-Te Lin
chrome-internal-fetch
parent
9caccd1e86
commit
a1cbc00aa8
14 changed files with 1653 additions and 1059 deletions
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@ -86,21 +86,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 1
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choice
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prompt "BCT sdram configuration"
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default NYAN_BIG_BCT_SDRAM_204
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help
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The SDRAM configuration to put in the BCT.
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config NYAN_BIG_BCT_SDRAM_204
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bool "204 MHz"
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config NYAN_BIG_BCT_SDRAM_792
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bool "792 MHz"
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config NYAN_BIG_BCT_SDRAM_924
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bool "924 MHz"
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endchoice
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endif # BOARD_GOOGLE_NYAN_BIG
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@ -32,5 +32,6 @@ bootblock-y += bootblock.c
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bootblock-y += pmic.c
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romstage-y += romstage.c
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romstage-y += sdram_configs.c
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ramstage-y += mainboard.c
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@ -20,6 +20,7 @@
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bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg
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bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg
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bct-cfg-y += odmdata.cfg
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bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_204) += sdram-204.cfg
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bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg
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bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg
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# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
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# the include files (sdram-*.inc). See ../../nyan/bct/Makefile.inc for more
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# information.
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311
src/mainboard/google/nyan_big/bct/sdram-0001-204-2GB.inc
Normal file
311
src/mainboard/google/nyan_big/bct/sdram-0001-204-2GB.inc
Normal file
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@ -0,0 +1,311 @@
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{ /* generated from sdram-0001-204-2GB.cfg; do not edit. */
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.MemoryType = NvBootMemoryType_Ddr3,
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.PllMInputDivider = 0x00000001,
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.PllMFeedbackDivider = 0x00000022,
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.PllMStableTime = 0x0000012c,
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.PllMSetupControl = 0x00000000,
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.PllMSelectDiv2 = 0x00000000,
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.PllMPDLshiftPh45 = 0x00000001,
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.PllMPDLshiftPh90 = 0x00000001,
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.PllMPDLshiftPh135 = 0x00000001,
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.PllMKCP = 0x00000000,
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.PllMKVCO = 0x00000000,
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.EmcBctSpare0 = 0x00000000,
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.EmcBctSpare1 = 0x00000000,
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.EmcBctSpare2 = 0x00000000,
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.EmcBctSpare3 = 0x00000000,
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.EmcBctSpare4 = 0x00000000,
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.EmcBctSpare5 = 0x00000000,
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.EmcBctSpare6 = 0x00000000,
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.EmcBctSpare7 = 0x00000000,
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.EmcBctSpare8 = 0x00000000,
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.EmcBctSpare9 = 0x00000000,
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.EmcBctSpare10 = 0x00000000,
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.EmcBctSpare11 = 0x00000000,
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.EmcClockSource = 0x40000002,
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.EmcAutoCalInterval = 0x001fffff,
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.EmcAutoCalConfig = 0xa1430000,
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.EmcAutoCalConfig2 = 0x00000000,
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.EmcAutoCalConfig3 = 0x00000000,
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.EmcAutoCalWait = 0x00000190,
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.EmcAdrCfg = 0x00000000,
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.EmcPinProgramWait = 0x00000001,
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.EmcPinExtraWait = 0x00000000,
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.EmcTimingControlWait = 0x00000000,
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.EmcRc = 0x00000009,
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.EmcRfc = 0x00000035,
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.EmcRfcSlr = 0x00000000,
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.EmcRas = 0x00000007,
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.EmcRp = 0x00000002,
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.EmcR2r = 0x00000000,
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.EmcW2w = 0x00000000,
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.EmcR2w = 0x00000005,
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.EmcW2r = 0x0000000a,
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.EmcR2p = 0x00000003,
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.EmcW2p = 0x0000000b,
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.EmcRdRcd = 0x00000002,
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.EmcWrRcd = 0x00000002,
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.EmcRrd = 0x00000003,
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.EmcRext = 0x00000003,
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.EmcWext = 0x00000000,
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.EmcWdv = 0x00000005,
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.EmcWdvMask = 0x00000005,
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.EmcQUse = 0x00000006,
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.EmcQuseWidth = 0x00000002,
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.EmcIbdly = 0x00000000,
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.EmcEInput = 0x00000004,
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.EmcEInputDuration = 0x00000006,
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.EmcPutermExtra = 0x00010000,
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.EmcPutermWidth = 0x00000003,
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.EmcPutermAdj = 0x00000000,
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.EmcCdbCntl1 = 0x00000000,
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.EmcCdbCntl2 = 0x00000000,
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.EmcCdbCntl3 = 0x00000000,
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.EmcQRst = 0x00000003,
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.EmcQSafe = 0x0000000d,
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.EmcRdv = 0x0000000f,
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.EmcRdvMask = 0x00000011,
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.EmcQpop = 0x0000000a,
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.EmcCtt = 0x00000000,
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.EmcCttDuration = 0x00000003,
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.EmcRefresh = 0x00000607,
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.EmcBurstRefreshNum = 0x00000000,
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.EmcPreRefreshReqCnt = 0x00000181,
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.EmcPdEx2Wr = 0x00000002,
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.EmcPdEx2Rd = 0x00000002,
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.EmcPChg2Pden = 0x00000001,
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.EmcAct2Pden = 0x00000000,
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.EmcAr2Pden = 0x00000032,
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.EmcRw2Pden = 0x0000000f,
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.EmcTxsr = 0x00000038,
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.EmcTxsrDll = 0x00000038,
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.EmcTcke = 0x00000004,
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.EmcTckesr = 0x00000005,
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.EmcTpd = 0x00000004,
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.EmcTfaw = 0x00000007,
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.EmcTrpab = 0x00000000,
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.EmcTClkStable = 0x00000005,
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.EmcTClkStop = 0x00000005,
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.EmcTRefBw = 0x00000638,
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.EmcFbioCfg5 = 0x106aa298,
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.EmcFbioCfg6 = 0x00000000,
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.EmcFbioSpare = 0x00000000,
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.EmcCfgRsv = 0xff00ff00,
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.EmcMrs = 0x80001221,
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.EmcEmrs = 0x80100003,
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.EmcEmrs2 = 0x80200008,
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.EmcEmrs3 = 0x80300000,
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.EmcMrw1 = 0x00000000,
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.EmcMrw2 = 0x00000000,
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.EmcMrw3 = 0x00000000,
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.EmcMrw4 = 0x00000000,
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.EmcMrwExtra = 0x00000000,
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.EmcWarmBootMrwExtra = 0x00000000,
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.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
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.EmcExtraModeRegWriteEnable = 0x00000000,
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.EmcMrwResetCommand = 0x00000000,
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.EmcMrwResetNInitWait = 0x00000000,
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.EmcMrsWaitCnt = 0x000c000c,
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.EmcMrsWaitCnt2 = 0x000c000c,
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.EmcCfg = 0x73240000,
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.EmcCfg2 = 0x0000088d,
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.EmcCfgPipe = 0x0000d2b3,
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.EmcDbg = 0x01000c00,
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.EmcCmdQ = 0x10004408,
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.EmcMc2EmcQ = 0x06000404,
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.EmcDynSelfRefControl = 0x80000d22,
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.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
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.EmcCfgDigDll = 0x002c00a0,
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.EmcCfgDigDllPeriod = 0x00008000,
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.EmcDevSelect = 0x00000002,
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.EmcSelDpdCtrl = 0x00040008,
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.EmcDllXformDqs0 = 0x00064000,
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.EmcDllXformDqs1 = 0x00064000,
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.EmcDllXformDqs2 = 0x00064000,
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.EmcDllXformDqs3 = 0x00064000,
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.EmcDllXformDqs4 = 0x00064000,
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.EmcDllXformDqs5 = 0x00064000,
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.EmcDllXformDqs6 = 0x00064000,
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.EmcDllXformDqs7 = 0x00064000,
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.EmcDllXformDqs8 = 0x00064000,
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.EmcDllXformDqs9 = 0x00064000,
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.EmcDllXformDqs10 = 0x00064000,
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.EmcDllXformDqs11 = 0x00064000,
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.EmcDllXformDqs12 = 0x00064000,
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.EmcDllXformDqs13 = 0x00064000,
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.EmcDllXformDqs14 = 0x00064000,
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.EmcDllXformDqs15 = 0x00064000,
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.EmcDllXformQUse0 = 0x00000000,
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.EmcDllXformQUse1 = 0x00000000,
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.EmcDllXformQUse2 = 0x00000000,
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.EmcDllXformQUse3 = 0x00000000,
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.EmcDllXformQUse4 = 0x00000000,
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.EmcDllXformQUse5 = 0x00000000,
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.EmcDllXformQUse6 = 0x00000000,
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.EmcDllXformQUse7 = 0x00000000,
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.EmcDllXformAddr0 = 0x00000000,
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.EmcDllXformAddr1 = 0x00000000,
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.EmcDllXformAddr2 = 0x00004000,
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.EmcDllXformAddr3 = 0x00000000,
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.EmcDllXformAddr4 = 0x00000000,
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.EmcDllXformAddr5 = 0x00004000,
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.EmcDllXformQUse8 = 0x00000000,
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.EmcDllXformQUse9 = 0x00000000,
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.EmcDllXformQUse10 = 0x00000000,
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.EmcDllXformQUse11 = 0x00000000,
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.EmcDllXformQUse12 = 0x00000000,
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.EmcDllXformQUse13 = 0x00000000,
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.EmcDllXformQUse14 = 0x00000000,
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.EmcDllXformQUse15 = 0x00000000,
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.EmcDliTrimTxDqs0 = 0x00000000,
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.EmcDliTrimTxDqs1 = 0x00000000,
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.EmcDliTrimTxDqs2 = 0x00000000,
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.EmcDliTrimTxDqs3 = 0x00000000,
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.EmcDliTrimTxDqs4 = 0x00000000,
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.EmcDliTrimTxDqs5 = 0x00000000,
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.EmcDliTrimTxDqs6 = 0x00000000,
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.EmcDliTrimTxDqs7 = 0x00000000,
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.EmcDliTrimTxDqs8 = 0x00000000,
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.EmcDliTrimTxDqs9 = 0x00000000,
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.EmcDliTrimTxDqs10 = 0x00000000,
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.EmcDliTrimTxDqs11 = 0x00000000,
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.EmcDliTrimTxDqs12 = 0x00000000,
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.EmcDliTrimTxDqs13 = 0x00000000,
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.EmcDliTrimTxDqs14 = 0x00000000,
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.EmcDliTrimTxDqs15 = 0x00000000,
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.EmcDllXformDq0 = 0x00090000,
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.EmcDllXformDq1 = 0x00090000,
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.EmcDllXformDq2 = 0x00094000,
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.EmcDllXformDq3 = 0x00094000,
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.EmcDllXformDq4 = 0x00009400,
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.EmcDllXformDq5 = 0x00009000,
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.EmcDllXformDq6 = 0x00009000,
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.EmcDllXformDq7 = 0x00009000,
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.WarmBootWait = 0x00000002,
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.EmcCttTermCtrl = 0x00000802,
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.EmcOdtWrite = 0x00000000,
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.EmcOdtRead = 0x00000000,
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.EmcZcalInterval = 0x00020000,
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.EmcZcalWaitCnt = 0x00000042,
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.EmcZcalMrwCmd = 0x80000000,
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.EmcMrsResetDll = 0x00000000,
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.EmcZcalInitDev0 = 0x80000011,
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.EmcZcalInitDev1 = 0x00000000,
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.EmcZcalInitWait = 0x00000003,
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.EmcZcalWarmColdBootEnables = 0x00000003,
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.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
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.EmcZqCalDdr3WarmBoot = 0x00000000,
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.EmcZcalWarmBootWait = 0x00000002,
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.EmcMrsWarmBootEnable = 0x00000001,
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.EmcMrsResetDllWait = 0x00000000,
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.EmcMrsExtra = 0x80001221,
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.EmcWarmBootMrsExtra = 0x80100003,
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.EmcEmrsDdr2DllEnable = 0x00000000,
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.EmcMrsDdr2DllReset = 0x00000000,
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.EmcEmrsDdr2OcdCalib = 0x00000000,
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.EmcDdr2Wait = 0x00000000,
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.EmcClkenOverride = 0x00000000,
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.McDisExtraSnapLevels = 0x00000000,
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.EmcExtraRefreshNum = 0x00000002,
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.EmcClkenOverrideAllWarmBoot = 0x00000000,
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.McClkenOverrideAllWarmBoot = 0x00000000,
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.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
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.PmcVddpSel = 0x00000002,
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.PmcVddpSelWait = 0x00000002,
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.PmcDdrPwr = 0x00000003,
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.PmcDdrCfg = 0x00002002,
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.PmcIoDpd3Req = 0x4fff2f97,
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.PmcIoDpd3ReqWait = 0x00000000,
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.PmcRegShort = 0x00000000,
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.PmcNoIoPower = 0x00000000,
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.PmcPorDpdCtrlWait = 0x00000000,
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.EmcXm2CmdPadCtrl = 0x10000280,
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.EmcXm2CmdPadCtrl2 = 0x770c0000,
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.EmcXm2CmdPadCtrl3 = 0x050c0000,
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.EmcXm2CmdPadCtrl4 = 0x00000000,
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.EmcXm2CmdPadCtrl5 = 0x00111111,
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.EmcXm2DqsPadCtrl = 0x770c1414,
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.EmcXm2DqsPadCtrl2 = 0x0130b118,
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.EmcXm2DqsPadCtrl3 = 0x51451400,
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.EmcXm2DqsPadCtrl4 = 0x00514514,
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.EmcXm2DqsPadCtrl5 = 0x00514514,
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.EmcXm2DqsPadCtrl6 = 0x51451400,
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.EmcXm2DqPadCtrl = 0x770c2990,
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.EmcXm2DqPadCtrl2 = 0x00000000,
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.EmcXm2DqPadCtrl3 = 0x00000000,
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.EmcXm2ClkPadCtrl = 0x77ffc081,
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.EmcXm2ClkPadCtrl2 = 0x00000303,
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.EmcXm2CompPadCtrl = 0x81f1f108,
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.EmcXm2VttGenPadCtrl = 0x07070004,
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.EmcXm2VttGenPadCtrl2 = 0x0000003f,
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.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
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.EmcAcpdControl = 0x00000000,
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.EmcSwizzleRank0ByteCfg = 0x00003120,
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.EmcSwizzleRank0Byte0 = 0x25143067,
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.EmcSwizzleRank0Byte1 = 0x45367102,
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.EmcSwizzleRank0Byte2 = 0x47106253,
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.EmcSwizzleRank0Byte3 = 0x04362175,
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.EmcSwizzleRank1ByteCfg = 0x00003120,
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.EmcSwizzleRank1Byte0 = 0x71546032,
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.EmcSwizzleRank1Byte1 = 0x35104276,
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.EmcSwizzleRank1Byte2 = 0x27043615,
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.EmcSwizzleRank1Byte3 = 0x72306145,
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.EmcDsrVttgenDrv = 0x0000003f,
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.EmcTxdsrvttgen = 0x00000066,
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.EmcBgbiasCtl0 = 0x00000008,
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.McEmemAdrCfg = 0x00000000,
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.McEmemAdrCfgDev0 = 0x00080303,
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.McEmemAdrCfgDev1 = 0x00080303,
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.McEmemAdrCfgBankMask0 = 0x00001248,
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.McEmemAdrCfgBankMask1 = 0x00002490,
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.McEmemAdrCfgBankMask2 = 0x00000920,
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.McEmemAdrCfgBankSwizzle3 = 0x00000001,
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.McEmemCfg = 0x00000800,
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.McEmemArbCfg = 0x01000003,
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.McEmemArbOutstandingReq = 0x80000040,
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.McEmemArbTimingRcd = 0x00000001,
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.McEmemArbTimingRp = 0x00000001,
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.McEmemArbTimingRc = 0x00000005,
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.McEmemArbTimingRas = 0x00000002,
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.McEmemArbTimingFaw = 0x00000004,
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.McEmemArbTimingRrd = 0x00000001,
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.McEmemArbTimingRap2Pre = 0x00000002,
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.McEmemArbTimingWap2Pre = 0x00000008,
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.McEmemArbTimingR2R = 0x00000003,
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.McEmemArbTimingW2W = 0x00000002,
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.McEmemArbTimingR2W = 0x00000004,
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.McEmemArbTimingW2R = 0x00000006,
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.McEmemArbDaTurns = 0x06040203,
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.McEmemArbDaCovers = 0x000a0405,
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.McEmemArbMisc0 = 0x73840a06,
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.McEmemArbMisc1 = 0x70000f03,
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.McEmemArbRing1Throttle = 0x001f0000,
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.McEmemArbOverride = 0x10000000,
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.McEmemArbOverride1 = 0x00000000,
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.McEmemArbRsv = 0xff00ff00,
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.McClkenOverride = 0x00000000,
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.McStatControl = 0x00000000,
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.McDisplaySnapRing = 0x00000003,
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.McVideoProtectBom = 0xfff00000,
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.McVideoProtectBomAdrHi = 0x00000000,
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.McVideoProtectSizeMb = 0x00000000,
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.McVideoProtectVprOverride = 0xe4bac743,
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.McVideoProtectVprOverride1 = 0x00000013,
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.McVideoProtectGpuOverride0 = 0x00000000,
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.McVideoProtectGpuOverride1 = 0x00000000,
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.McSecCarveoutBom = 0xfff00000,
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.McSecCarveoutAdrHi = 0x00000000,
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.McSecCarveoutSizeMb = 0x00000000,
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.McVideoProtectWriteAccess = 0x00000000,
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.McSecCarveoutProtectWriteAccess = 0x00000000,
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.EmcCaTrainingEnable = 0x00000000,
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.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
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.EmcCaTrainingTimingCntl2 = 0x0000001f,
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.SwizzleRankByteEncode = 0x0000006f,
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.BootRomPatchControl = 0x00000000,
|
||||
.BootRomPatchData = 0x00000000,
|
||||
.McMtsCarveoutBom = 0xfff00000,
|
||||
.McMtsCarveoutAdrHi = 0x00000000,
|
||||
.McMtsCarveoutSizeMb = 0x00000000,
|
||||
.McMtsCarveoutRegCtrl = 0x00000000,
|
||||
},
|
||||
311
src/mainboard/google/nyan_big/bct/sdram-0001-792-2GB.inc
Normal file
311
src/mainboard/google/nyan_big/bct/sdram-0001-792-2GB.inc
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
|
||||
.MemoryType = NvBootMemoryType_Ddr3,
|
||||
.PllMInputDivider = 0x00000001,
|
||||
.PllMFeedbackDivider = 0x00000042,
|
||||
.PllMStableTime = 0x0000012c,
|
||||
.PllMSetupControl = 0x00000000,
|
||||
.PllMSelectDiv2 = 0x00000000,
|
||||
.PllMPDLshiftPh45 = 0x00000001,
|
||||
.PllMPDLshiftPh90 = 0x00000001,
|
||||
.PllMPDLshiftPh135 = 0x00000001,
|
||||
.PllMKCP = 0x00000000,
|
||||
.PllMKVCO = 0x00000000,
|
||||
.EmcBctSpare0 = 0x00000000,
|
||||
.EmcBctSpare1 = 0x00000000,
|
||||
.EmcBctSpare2 = 0x00000000,
|
||||
.EmcBctSpare3 = 0x00000000,
|
||||
.EmcBctSpare4 = 0x00000000,
|
||||
.EmcBctSpare5 = 0x00000000,
|
||||
.EmcBctSpare6 = 0x00000000,
|
||||
.EmcBctSpare7 = 0x00000000,
|
||||
.EmcBctSpare8 = 0x00000000,
|
||||
.EmcBctSpare9 = 0x00000000,
|
||||
.EmcBctSpare10 = 0x00000000,
|
||||
.EmcBctSpare11 = 0x00000000,
|
||||
.EmcClockSource = 0x80000000,
|
||||
.EmcAutoCalInterval = 0x001fffff,
|
||||
.EmcAutoCalConfig = 0xa1430000,
|
||||
.EmcAutoCalConfig2 = 0x00000000,
|
||||
.EmcAutoCalConfig3 = 0x00000000,
|
||||
.EmcAutoCalWait = 0x00000190,
|
||||
.EmcAdrCfg = 0x00000000,
|
||||
.EmcPinProgramWait = 0x00000001,
|
||||
.EmcPinExtraWait = 0x00000000,
|
||||
.EmcTimingControlWait = 0x00000000,
|
||||
.EmcRc = 0x00000025,
|
||||
.EmcRfc = 0x000000cc,
|
||||
.EmcRfcSlr = 0x00000000,
|
||||
.EmcRas = 0x0000001a,
|
||||
.EmcRp = 0x00000009,
|
||||
.EmcR2r = 0x00000000,
|
||||
.EmcW2w = 0x00000000,
|
||||
.EmcR2w = 0x00000008,
|
||||
.EmcW2r = 0x0000000d,
|
||||
.EmcR2p = 0x00000004,
|
||||
.EmcW2p = 0x00000013,
|
||||
.EmcRdRcd = 0x00000009,
|
||||
.EmcWrRcd = 0x00000009,
|
||||
.EmcRrd = 0x00000003,
|
||||
.EmcRext = 0x00000002,
|
||||
.EmcWext = 0x00000000,
|
||||
.EmcWdv = 0x00000006,
|
||||
.EmcWdvMask = 0x00000006,
|
||||
.EmcQUse = 0x0000000b,
|
||||
.EmcQuseWidth = 0x00000002,
|
||||
.EmcIbdly = 0x00000000,
|
||||
.EmcEInput = 0x00000002,
|
||||
.EmcEInputDuration = 0x0000000d,
|
||||
.EmcPutermExtra = 0x00080000,
|
||||
.EmcPutermWidth = 0x00000004,
|
||||
.EmcPutermAdj = 0x00000000,
|
||||
.EmcCdbCntl1 = 0x00000000,
|
||||
.EmcCdbCntl2 = 0x00000000,
|
||||
.EmcCdbCntl3 = 0x00000000,
|
||||
.EmcQRst = 0x00000001,
|
||||
.EmcQSafe = 0x00000014,
|
||||
.EmcRdv = 0x00000018,
|
||||
.EmcRdvMask = 0x0000001a,
|
||||
.EmcQpop = 0x0000000f,
|
||||
.EmcCtt = 0x00000000,
|
||||
.EmcCttDuration = 0x00000004,
|
||||
.EmcRefresh = 0x000017e2,
|
||||
.EmcBurstRefreshNum = 0x00000000,
|
||||
.EmcPreRefreshReqCnt = 0x000005f8,
|
||||
.EmcPdEx2Wr = 0x00000003,
|
||||
.EmcPdEx2Rd = 0x00000011,
|
||||
.EmcPChg2Pden = 0x00000001,
|
||||
.EmcAct2Pden = 0x00000000,
|
||||
.EmcAr2Pden = 0x000000c6,
|
||||
.EmcRw2Pden = 0x00000018,
|
||||
.EmcTxsr = 0x000000d6,
|
||||
.EmcTxsrDll = 0x00000200,
|
||||
.EmcTcke = 0x00000005,
|
||||
.EmcTckesr = 0x00000006,
|
||||
.EmcTpd = 0x00000005,
|
||||
.EmcTfaw = 0x0000001d,
|
||||
.EmcTrpab = 0x00000000,
|
||||
.EmcTClkStable = 0x00000008,
|
||||
.EmcTClkStop = 0x00000008,
|
||||
.EmcTRefBw = 0x00001822,
|
||||
.EmcFbioCfg5 = 0x104ab098,
|
||||
.EmcFbioCfg6 = 0x00000000,
|
||||
.EmcFbioSpare = 0x00000000,
|
||||
.EmcCfgRsv = 0xff00ff00,
|
||||
.EmcMrs = 0x80000d71,
|
||||
.EmcEmrs = 0x80100002,
|
||||
.EmcEmrs2 = 0x80200018,
|
||||
.EmcEmrs3 = 0x80300000,
|
||||
.EmcMrw1 = 0x00000000,
|
||||
.EmcMrw2 = 0x00000000,
|
||||
.EmcMrw3 = 0x00000000,
|
||||
.EmcMrw4 = 0x00000000,
|
||||
.EmcMrwExtra = 0x00000000,
|
||||
.EmcWarmBootMrwExtra = 0x00000000,
|
||||
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcMrwResetCommand = 0x00000000,
|
||||
.EmcMrwResetNInitWait = 0x00000000,
|
||||
.EmcMrsWaitCnt = 0x00f8000c,
|
||||
.EmcMrsWaitCnt2 = 0x00f8000c,
|
||||
.EmcCfg = 0x73300000,
|
||||
.EmcCfg2 = 0x0000089d,
|
||||
.EmcCfgPipe = 0x00004080,
|
||||
.EmcDbg = 0x01000c00,
|
||||
.EmcCmdQ = 0x10004408,
|
||||
.EmcMc2EmcQ = 0x06000404,
|
||||
.EmcDynSelfRefControl = 0x80003012,
|
||||
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
|
||||
.EmcCfgDigDll = 0xe00700b1,
|
||||
.EmcCfgDigDllPeriod = 0x00008000,
|
||||
.EmcDevSelect = 0x00000002,
|
||||
.EmcSelDpdCtrl = 0x00040000,
|
||||
.EmcDllXformDqs0 = 0x00000008,
|
||||
.EmcDllXformDqs1 = 0x00000008,
|
||||
.EmcDllXformDqs2 = 0x00000008,
|
||||
.EmcDllXformDqs3 = 0x00000008,
|
||||
.EmcDllXformDqs4 = 0x00000008,
|
||||
.EmcDllXformDqs5 = 0x00000008,
|
||||
.EmcDllXformDqs6 = 0x00000008,
|
||||
.EmcDllXformDqs7 = 0x00000008,
|
||||
.EmcDllXformDqs8 = 0x00000008,
|
||||
.EmcDllXformDqs9 = 0x00000008,
|
||||
.EmcDllXformDqs10 = 0x00000008,
|
||||
.EmcDllXformDqs11 = 0x00000008,
|
||||
.EmcDllXformDqs12 = 0x00000008,
|
||||
.EmcDllXformDqs13 = 0x00000008,
|
||||
.EmcDllXformDqs14 = 0x00000008,
|
||||
.EmcDllXformDqs15 = 0x00000008,
|
||||
.EmcDllXformQUse0 = 0x00000000,
|
||||
.EmcDllXformQUse1 = 0x00000000,
|
||||
.EmcDllXformQUse2 = 0x00000000,
|
||||
.EmcDllXformQUse3 = 0x00000000,
|
||||
.EmcDllXformQUse4 = 0x00000000,
|
||||
.EmcDllXformQUse5 = 0x00000000,
|
||||
.EmcDllXformQUse6 = 0x00000000,
|
||||
.EmcDllXformQUse7 = 0x00000000,
|
||||
.EmcDllXformAddr0 = 0x00034000,
|
||||
.EmcDllXformAddr1 = 0x00034000,
|
||||
.EmcDllXformAddr2 = 0x00000000,
|
||||
.EmcDllXformAddr3 = 0x00034000,
|
||||
.EmcDllXformAddr4 = 0x00034000,
|
||||
.EmcDllXformAddr5 = 0x00000000,
|
||||
.EmcDllXformQUse8 = 0x00000000,
|
||||
.EmcDllXformQUse9 = 0x00000000,
|
||||
.EmcDllXformQUse10 = 0x00000000,
|
||||
.EmcDllXformQUse11 = 0x00000000,
|
||||
.EmcDllXformQUse12 = 0x00000000,
|
||||
.EmcDllXformQUse13 = 0x00000000,
|
||||
.EmcDllXformQUse14 = 0x00000000,
|
||||
.EmcDllXformQUse15 = 0x00000000,
|
||||
.EmcDliTrimTxDqs0 = 0x00000008,
|
||||
.EmcDliTrimTxDqs1 = 0x00000008,
|
||||
.EmcDliTrimTxDqs2 = 0x00000005,
|
||||
.EmcDliTrimTxDqs3 = 0x00000009,
|
||||
.EmcDliTrimTxDqs4 = 0x00000009,
|
||||
.EmcDliTrimTxDqs5 = 0x00000007,
|
||||
.EmcDliTrimTxDqs6 = 0x00000009,
|
||||
.EmcDliTrimTxDqs7 = 0x00000008,
|
||||
.EmcDliTrimTxDqs8 = 0x00000008,
|
||||
.EmcDliTrimTxDqs9 = 0x00000008,
|
||||
.EmcDliTrimTxDqs10 = 0x00000005,
|
||||
.EmcDliTrimTxDqs11 = 0x00000009,
|
||||
.EmcDliTrimTxDqs12 = 0x00000009,
|
||||
.EmcDliTrimTxDqs13 = 0x00000007,
|
||||
.EmcDliTrimTxDqs14 = 0x00000009,
|
||||
.EmcDliTrimTxDqs15 = 0x00000008,
|
||||
.EmcDllXformDq0 = 0x0000000e,
|
||||
.EmcDllXformDq1 = 0x0000000e,
|
||||
.EmcDllXformDq2 = 0x0000000e,
|
||||
.EmcDllXformDq3 = 0x0000000e,
|
||||
.EmcDllXformDq4 = 0x0000000e,
|
||||
.EmcDllXformDq5 = 0x0000000e,
|
||||
.EmcDllXformDq6 = 0x0000000e,
|
||||
.EmcDllXformDq7 = 0x0000000e,
|
||||
.WarmBootWait = 0x00000002,
|
||||
.EmcCttTermCtrl = 0x00000802,
|
||||
.EmcOdtWrite = 0x00000000,
|
||||
.EmcOdtRead = 0x00000000,
|
||||
.EmcZcalInterval = 0x00020000,
|
||||
.EmcZcalWaitCnt = 0x00000042,
|
||||
.EmcZcalMrwCmd = 0x80000000,
|
||||
.EmcMrsResetDll = 0x00000000,
|
||||
.EmcZcalInitDev0 = 0x80000011,
|
||||
.EmcZcalInitDev1 = 0x00000000,
|
||||
.EmcZcalInitWait = 0x00000001,
|
||||
.EmcZcalWarmColdBootEnables = 0x00000003,
|
||||
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
|
||||
.EmcZqCalDdr3WarmBoot = 0x00000000,
|
||||
.EmcZcalWarmBootWait = 0x00000001,
|
||||
.EmcMrsWarmBootEnable = 0x00000001,
|
||||
.EmcMrsResetDllWait = 0x00000000,
|
||||
.EmcMrsExtra = 0x80000d71,
|
||||
.EmcWarmBootMrsExtra = 0x80100002,
|
||||
.EmcEmrsDdr2DllEnable = 0x00000000,
|
||||
.EmcMrsDdr2DllReset = 0x00000000,
|
||||
.EmcEmrsDdr2OcdCalib = 0x00000000,
|
||||
.EmcDdr2Wait = 0x00000000,
|
||||
.EmcClkenOverride = 0x00000000,
|
||||
.McDisExtraSnapLevels = 0x00000000,
|
||||
.EmcExtraRefreshNum = 0x00000002,
|
||||
.EmcClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.McClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
|
||||
.PmcVddpSel = 0x00000002,
|
||||
.PmcVddpSelWait = 0x00000002,
|
||||
.PmcDdrPwr = 0x00000003,
|
||||
.PmcDdrCfg = 0x00002002,
|
||||
.PmcIoDpd3Req = 0x4fff2f97,
|
||||
.PmcIoDpd3ReqWait = 0x00000000,
|
||||
.PmcRegShort = 0x00000000,
|
||||
.PmcNoIoPower = 0x00000000,
|
||||
.PmcPorDpdCtrlWait = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl = 0x100002a0,
|
||||
.EmcXm2CmdPadCtrl2 = 0x770c0000,
|
||||
.EmcXm2CmdPadCtrl3 = 0x050c0000,
|
||||
.EmcXm2CmdPadCtrl4 = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl5 = 0x00111111,
|
||||
.EmcXm2DqsPadCtrl = 0x770c1414,
|
||||
.EmcXm2DqsPadCtrl2 = 0x0120113d,
|
||||
.EmcXm2DqsPadCtrl3 = 0x61861820,
|
||||
.EmcXm2DqsPadCtrl4 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl5 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl6 = 0x61861800,
|
||||
.EmcXm2DqPadCtrl = 0x770c2990,
|
||||
.EmcXm2DqPadCtrl2 = 0x00000000,
|
||||
.EmcXm2DqPadCtrl3 = 0x00000000,
|
||||
.EmcXm2ClkPadCtrl = 0x77ffc085,
|
||||
.EmcXm2ClkPadCtrl2 = 0x00000101,
|
||||
.EmcXm2CompPadCtrl = 0x81f1f108,
|
||||
.EmcXm2VttGenPadCtrl = 0x07070004,
|
||||
.EmcXm2VttGenPadCtrl2 = 0x00000000,
|
||||
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
|
||||
.EmcAcpdControl = 0x00000000,
|
||||
.EmcSwizzleRank0ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank0Byte0 = 0x25143067,
|
||||
.EmcSwizzleRank0Byte1 = 0x45367102,
|
||||
.EmcSwizzleRank0Byte2 = 0x47106253,
|
||||
.EmcSwizzleRank0Byte3 = 0x04362175,
|
||||
.EmcSwizzleRank1ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank1Byte0 = 0x71546032,
|
||||
.EmcSwizzleRank1Byte1 = 0x35104276,
|
||||
.EmcSwizzleRank1Byte2 = 0x27043615,
|
||||
.EmcSwizzleRank1Byte3 = 0x72306145,
|
||||
.EmcDsrVttgenDrv = 0x0606003f,
|
||||
.EmcTxdsrvttgen = 0x00000000,
|
||||
.EmcBgbiasCtl0 = 0x00000000,
|
||||
.McEmemAdrCfg = 0x00000000,
|
||||
.McEmemAdrCfgDev0 = 0x00080303,
|
||||
.McEmemAdrCfgDev1 = 0x00080303,
|
||||
.McEmemAdrCfgBankMask0 = 0x00001248,
|
||||
.McEmemAdrCfgBankMask1 = 0x00002490,
|
||||
.McEmemAdrCfgBankMask2 = 0x00000920,
|
||||
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
|
||||
.McEmemCfg = 0x00000800,
|
||||
.McEmemArbCfg = 0x0e00000b,
|
||||
.McEmemArbOutstandingReq = 0x80000040,
|
||||
.McEmemArbTimingRcd = 0x00000004,
|
||||
.McEmemArbTimingRp = 0x00000005,
|
||||
.McEmemArbTimingRc = 0x00000013,
|
||||
.McEmemArbTimingRas = 0x0000000c,
|
||||
.McEmemArbTimingFaw = 0x0000000f,
|
||||
.McEmemArbTimingRrd = 0x00000002,
|
||||
.McEmemArbTimingRap2Pre = 0x00000003,
|
||||
.McEmemArbTimingWap2Pre = 0x0000000c,
|
||||
.McEmemArbTimingR2R = 0x00000002,
|
||||
.McEmemArbTimingW2W = 0x00000002,
|
||||
.McEmemArbTimingR2W = 0x00000006,
|
||||
.McEmemArbTimingW2R = 0x00000008,
|
||||
.McEmemArbDaTurns = 0x08060202,
|
||||
.McEmemArbDaCovers = 0x00160d13,
|
||||
.McEmemArbMisc0 = 0x734c2414,
|
||||
.McEmemArbMisc1 = 0x70000f02,
|
||||
.McEmemArbRing1Throttle = 0x001f0000,
|
||||
.McEmemArbOverride = 0x10000000,
|
||||
.McEmemArbOverride1 = 0x00000000,
|
||||
.McEmemArbRsv = 0xff00ff00,
|
||||
.McClkenOverride = 0x00000000,
|
||||
.McStatControl = 0x00000000,
|
||||
.McDisplaySnapRing = 0x00000003,
|
||||
.McVideoProtectBom = 0xfff00000,
|
||||
.McVideoProtectBomAdrHi = 0x00000000,
|
||||
.McVideoProtectSizeMb = 0x00000000,
|
||||
.McVideoProtectVprOverride = 0xe4bac743,
|
||||
.McVideoProtectVprOverride1 = 0x00000013,
|
||||
.McVideoProtectGpuOverride0 = 0x00000000,
|
||||
.McVideoProtectGpuOverride1 = 0x00000000,
|
||||
.McSecCarveoutBom = 0xfff00000,
|
||||
.McSecCarveoutAdrHi = 0x00000000,
|
||||
.McSecCarveoutSizeMb = 0x00000000,
|
||||
.McVideoProtectWriteAccess = 0x00000000,
|
||||
.McSecCarveoutProtectWriteAccess = 0x00000000,
|
||||
.EmcCaTrainingEnable = 0x00000000,
|
||||
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
|
||||
.EmcCaTrainingTimingCntl2 = 0x0000001f,
|
||||
.SwizzleRankByteEncode = 0x0000006f,
|
||||
.BootRomPatchControl = 0x00000000,
|
||||
.BootRomPatchData = 0x00000000,
|
||||
.McMtsCarveoutBom = 0xfff00000,
|
||||
.McMtsCarveoutAdrHi = 0x00000000,
|
||||
.McMtsCarveoutSizeMb = 0x00000000,
|
||||
.McMtsCarveoutRegCtrl = 0x00000000,
|
||||
},
|
||||
311
src/mainboard/google/nyan_big/bct/sdram-0001-924-2GB.inc
Normal file
311
src/mainboard/google/nyan_big/bct/sdram-0001-924-2GB.inc
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */
|
||||
.MemoryType = NvBootMemoryType_Ddr3,
|
||||
.PllMInputDivider = 0x00000001,
|
||||
.PllMFeedbackDivider = 0x0000004d,
|
||||
.PllMStableTime = 0x0000012c,
|
||||
.PllMSetupControl = 0x00000000,
|
||||
.PllMSelectDiv2 = 0x00000000,
|
||||
.PllMPDLshiftPh45 = 0x00000001,
|
||||
.PllMPDLshiftPh90 = 0x00000001,
|
||||
.PllMPDLshiftPh135 = 0x00000001,
|
||||
.PllMKCP = 0x00000000,
|
||||
.PllMKVCO = 0x00000000,
|
||||
.EmcBctSpare0 = 0x00000000,
|
||||
.EmcBctSpare1 = 0x00000000,
|
||||
.EmcBctSpare2 = 0x00000000,
|
||||
.EmcBctSpare3 = 0x00000000,
|
||||
.EmcBctSpare4 = 0x00000000,
|
||||
.EmcBctSpare5 = 0x00000000,
|
||||
.EmcBctSpare6 = 0x00000000,
|
||||
.EmcBctSpare7 = 0x00000000,
|
||||
.EmcBctSpare8 = 0x00000000,
|
||||
.EmcBctSpare9 = 0x00000000,
|
||||
.EmcBctSpare10 = 0x00000000,
|
||||
.EmcBctSpare11 = 0x00000000,
|
||||
.EmcClockSource = 0x80000000,
|
||||
.EmcAutoCalInterval = 0x001fffff,
|
||||
.EmcAutoCalConfig = 0xa1430404,
|
||||
.EmcAutoCalConfig2 = 0x00000000,
|
||||
.EmcAutoCalConfig3 = 0x00000000,
|
||||
.EmcAutoCalWait = 0x00000190,
|
||||
.EmcAdrCfg = 0x00000000,
|
||||
.EmcPinProgramWait = 0x00000001,
|
||||
.EmcPinExtraWait = 0x00000000,
|
||||
.EmcTimingControlWait = 0x00000000,
|
||||
.EmcRc = 0x0000002b,
|
||||
.EmcRfc = 0x000000ef,
|
||||
.EmcRfcSlr = 0x00000000,
|
||||
.EmcRas = 0x0000001e,
|
||||
.EmcRp = 0x0000000b,
|
||||
.EmcR2r = 0x00000000,
|
||||
.EmcW2w = 0x00000000,
|
||||
.EmcR2w = 0x00000008,
|
||||
.EmcW2r = 0x0000000f,
|
||||
.EmcR2p = 0x00000005,
|
||||
.EmcW2p = 0x00000016,
|
||||
.EmcRdRcd = 0x0000000b,
|
||||
.EmcWrRcd = 0x0000000b,
|
||||
.EmcRrd = 0x00000004,
|
||||
.EmcRext = 0x00000002,
|
||||
.EmcWext = 0x00000000,
|
||||
.EmcWdv = 0x00000006,
|
||||
.EmcWdvMask = 0x00000006,
|
||||
.EmcQUse = 0x0000000c,
|
||||
.EmcQuseWidth = 0x00000002,
|
||||
.EmcIbdly = 0x00000000,
|
||||
.EmcEInput = 0x00000002,
|
||||
.EmcEInputDuration = 0x0000000e,
|
||||
.EmcPutermExtra = 0x000a0000,
|
||||
.EmcPutermWidth = 0x00000004,
|
||||
.EmcPutermAdj = 0x00000000,
|
||||
.EmcCdbCntl1 = 0x00000000,
|
||||
.EmcCdbCntl2 = 0x00000000,
|
||||
.EmcCdbCntl3 = 0x00000000,
|
||||
.EmcQRst = 0x00000001,
|
||||
.EmcQSafe = 0x00000015,
|
||||
.EmcRdv = 0x0000001b,
|
||||
.EmcRdvMask = 0x0000001d,
|
||||
.EmcQpop = 0x00000010,
|
||||
.EmcCtt = 0x00000000,
|
||||
.EmcCttDuration = 0x00000004,
|
||||
.EmcRefresh = 0x00001be9,
|
||||
.EmcBurstRefreshNum = 0x00000000,
|
||||
.EmcPreRefreshReqCnt = 0x000006fa,
|
||||
.EmcPdEx2Wr = 0x00000004,
|
||||
.EmcPdEx2Rd = 0x00000015,
|
||||
.EmcPChg2Pden = 0x00000001,
|
||||
.EmcAct2Pden = 0x00000000,
|
||||
.EmcAr2Pden = 0x000000e6,
|
||||
.EmcRw2Pden = 0x0000001b,
|
||||
.EmcTxsr = 0x000000fa,
|
||||
.EmcTxsrDll = 0x00000200,
|
||||
.EmcTcke = 0x00000006,
|
||||
.EmcTckesr = 0x00000007,
|
||||
.EmcTpd = 0x00000006,
|
||||
.EmcTfaw = 0x00000022,
|
||||
.EmcTrpab = 0x00000000,
|
||||
.EmcTClkStable = 0x0000000a,
|
||||
.EmcTClkStop = 0x0000000a,
|
||||
.EmcTRefBw = 0x00001c29,
|
||||
.EmcFbioCfg5 = 0x104ab898,
|
||||
.EmcFbioCfg6 = 0x00000002,
|
||||
.EmcFbioSpare = 0x00000000,
|
||||
.EmcCfgRsv = 0xff00ff00,
|
||||
.EmcMrs = 0x80000f15,
|
||||
.EmcEmrs = 0x80100002,
|
||||
.EmcEmrs2 = 0x80200020,
|
||||
.EmcEmrs3 = 0x80300000,
|
||||
.EmcMrw1 = 0x00000000,
|
||||
.EmcMrw2 = 0x00000000,
|
||||
.EmcMrw3 = 0x00000000,
|
||||
.EmcMrw4 = 0x00000000,
|
||||
.EmcMrwExtra = 0x00000000,
|
||||
.EmcWarmBootMrwExtra = 0x00000000,
|
||||
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcMrwResetCommand = 0x00000000,
|
||||
.EmcMrwResetNInitWait = 0x00000000,
|
||||
.EmcMrsWaitCnt = 0x00ce000e,
|
||||
.EmcMrsWaitCnt2 = 0x00ce000e,
|
||||
.EmcCfg = 0x73300000,
|
||||
.EmcCfg2 = 0x000008a5,
|
||||
.EmcCfgPipe = 0x00000000,
|
||||
.EmcDbg = 0x01000c00,
|
||||
.EmcCmdQ = 0x10004408,
|
||||
.EmcMc2EmcQ = 0x06000404,
|
||||
.EmcDynSelfRefControl = 0x800037ed,
|
||||
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
|
||||
.EmcCfgDigDll = 0xe00401b1,
|
||||
.EmcCfgDigDllPeriod = 0x00008000,
|
||||
.EmcDevSelect = 0x00000002,
|
||||
.EmcSelDpdCtrl = 0x00040000,
|
||||
.EmcDllXformDqs0 = 0x00000005,
|
||||
.EmcDllXformDqs1 = 0x00000005,
|
||||
.EmcDllXformDqs2 = 0x00000005,
|
||||
.EmcDllXformDqs3 = 0x00000005,
|
||||
.EmcDllXformDqs4 = 0x00000005,
|
||||
.EmcDllXformDqs5 = 0x00000005,
|
||||
.EmcDllXformDqs6 = 0x00000005,
|
||||
.EmcDllXformDqs7 = 0x00000005,
|
||||
.EmcDllXformDqs8 = 0x00000005,
|
||||
.EmcDllXformDqs9 = 0x00000005,
|
||||
.EmcDllXformDqs10 = 0x00000005,
|
||||
.EmcDllXformDqs11 = 0x00000005,
|
||||
.EmcDllXformDqs12 = 0x00000005,
|
||||
.EmcDllXformDqs13 = 0x00000005,
|
||||
.EmcDllXformDqs14 = 0x00000005,
|
||||
.EmcDllXformDqs15 = 0x00000005,
|
||||
.EmcDllXformQUse0 = 0x00000000,
|
||||
.EmcDllXformQUse1 = 0x00000000,
|
||||
.EmcDllXformQUse2 = 0x00000000,
|
||||
.EmcDllXformQUse3 = 0x00000000,
|
||||
.EmcDllXformQUse4 = 0x00000000,
|
||||
.EmcDllXformQUse5 = 0x00000000,
|
||||
.EmcDllXformQUse6 = 0x00000000,
|
||||
.EmcDllXformQUse7 = 0x00000000,
|
||||
.EmcDllXformAddr0 = 0x0000400e,
|
||||
.EmcDllXformAddr1 = 0x0000400e,
|
||||
.EmcDllXformAddr2 = 0x00000000,
|
||||
.EmcDllXformAddr3 = 0x0000400e,
|
||||
.EmcDllXformAddr4 = 0x0000400e,
|
||||
.EmcDllXformAddr5 = 0x00000000,
|
||||
.EmcDllXformQUse8 = 0x00000000,
|
||||
.EmcDllXformQUse9 = 0x00000000,
|
||||
.EmcDllXformQUse10 = 0x00000000,
|
||||
.EmcDllXformQUse11 = 0x00000000,
|
||||
.EmcDllXformQUse12 = 0x00000000,
|
||||
.EmcDllXformQUse13 = 0x00000000,
|
||||
.EmcDllXformQUse14 = 0x00000000,
|
||||
.EmcDllXformQUse15 = 0x00000000,
|
||||
.EmcDliTrimTxDqs0 = 0x00000000,
|
||||
.EmcDliTrimTxDqs1 = 0x00000000,
|
||||
.EmcDliTrimTxDqs2 = 0x00000000,
|
||||
.EmcDliTrimTxDqs3 = 0x00000000,
|
||||
.EmcDliTrimTxDqs4 = 0x00000000,
|
||||
.EmcDliTrimTxDqs5 = 0x00000000,
|
||||
.EmcDliTrimTxDqs6 = 0x00000000,
|
||||
.EmcDliTrimTxDqs7 = 0x00000000,
|
||||
.EmcDliTrimTxDqs8 = 0x00000000,
|
||||
.EmcDliTrimTxDqs9 = 0x00000000,
|
||||
.EmcDliTrimTxDqs10 = 0x00000000,
|
||||
.EmcDliTrimTxDqs11 = 0x00000000,
|
||||
.EmcDliTrimTxDqs12 = 0x00000000,
|
||||
.EmcDliTrimTxDqs13 = 0x00000000,
|
||||
.EmcDliTrimTxDqs14 = 0x00000000,
|
||||
.EmcDliTrimTxDqs15 = 0x00000000,
|
||||
.EmcDllXformDq0 = 0x00000006,
|
||||
.EmcDllXformDq1 = 0x00000006,
|
||||
.EmcDllXformDq2 = 0x00000006,
|
||||
.EmcDllXformDq3 = 0x00000006,
|
||||
.EmcDllXformDq4 = 0x00000006,
|
||||
.EmcDllXformDq5 = 0x00000006,
|
||||
.EmcDllXformDq6 = 0x00000006,
|
||||
.EmcDllXformDq7 = 0x00000006,
|
||||
.WarmBootWait = 0x00000002,
|
||||
.EmcCttTermCtrl = 0x00000802,
|
||||
.EmcOdtWrite = 0x00000000,
|
||||
.EmcOdtRead = 0x00000000,
|
||||
.EmcZcalInterval = 0x00020000,
|
||||
.EmcZcalWaitCnt = 0x0000004c,
|
||||
.EmcZcalMrwCmd = 0x80000000,
|
||||
.EmcMrsResetDll = 0x00000000,
|
||||
.EmcZcalInitDev0 = 0x80000011,
|
||||
.EmcZcalInitDev1 = 0x00000000,
|
||||
.EmcZcalInitWait = 0x00000001,
|
||||
.EmcZcalWarmColdBootEnables = 0x00000003,
|
||||
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
|
||||
.EmcZqCalDdr3WarmBoot = 0x00000000,
|
||||
.EmcZcalWarmBootWait = 0x00000001,
|
||||
.EmcMrsWarmBootEnable = 0x00000001,
|
||||
.EmcMrsResetDllWait = 0x00000000,
|
||||
.EmcMrsExtra = 0x80000f15,
|
||||
.EmcWarmBootMrsExtra = 0x80100002,
|
||||
.EmcEmrsDdr2DllEnable = 0x00000000,
|
||||
.EmcMrsDdr2DllReset = 0x00000000,
|
||||
.EmcEmrsDdr2OcdCalib = 0x00000000,
|
||||
.EmcDdr2Wait = 0x00000000,
|
||||
.EmcClkenOverride = 0x00000000,
|
||||
.McDisExtraSnapLevels = 0x00000000,
|
||||
.EmcExtraRefreshNum = 0x00000002,
|
||||
.EmcClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.McClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
|
||||
.PmcVddpSel = 0x00000002,
|
||||
.PmcVddpSelWait = 0x00000002,
|
||||
.PmcDdrPwr = 0x00000003,
|
||||
.PmcDdrCfg = 0x00002002,
|
||||
.PmcIoDpd3Req = 0x4fff2f97,
|
||||
.PmcIoDpd3ReqWait = 0x00000000,
|
||||
.PmcRegShort = 0x00000000,
|
||||
.PmcNoIoPower = 0x00000000,
|
||||
.PmcPorDpdCtrlWait = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl = 0x100002a0,
|
||||
.EmcXm2CmdPadCtrl2 = 0x770c0000,
|
||||
.EmcXm2CmdPadCtrl3 = 0x050c0000,
|
||||
.EmcXm2CmdPadCtrl4 = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl5 = 0x00111111,
|
||||
.EmcXm2DqsPadCtrl = 0x770c1414,
|
||||
.EmcXm2DqsPadCtrl2 = 0x0020013d,
|
||||
.EmcXm2DqsPadCtrl3 = 0x55555520,
|
||||
.EmcXm2DqsPadCtrl4 = 0x003cf3cf,
|
||||
.EmcXm2DqsPadCtrl5 = 0x003cf3cf,
|
||||
.EmcXm2DqsPadCtrl6 = 0x55555500,
|
||||
.EmcXm2DqPadCtrl = 0x770c2990,
|
||||
.EmcXm2DqPadCtrl2 = 0x00000000,
|
||||
.EmcXm2DqPadCtrl3 = 0x00000000,
|
||||
.EmcXm2ClkPadCtrl = 0x77ffc085,
|
||||
.EmcXm2ClkPadCtrl2 = 0x00000303,
|
||||
.EmcXm2CompPadCtrl = 0x81f1f108,
|
||||
.EmcXm2VttGenPadCtrl = 0x07070004,
|
||||
.EmcXm2VttGenPadCtrl2 = 0x00000000,
|
||||
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
|
||||
.EmcAcpdControl = 0x00000000,
|
||||
.EmcSwizzleRank0ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank0Byte0 = 0x25143067,
|
||||
.EmcSwizzleRank0Byte1 = 0x45367102,
|
||||
.EmcSwizzleRank0Byte2 = 0x47106253,
|
||||
.EmcSwizzleRank0Byte3 = 0x04362175,
|
||||
.EmcSwizzleRank1ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank1Byte0 = 0x71546032,
|
||||
.EmcSwizzleRank1Byte1 = 0x35104276,
|
||||
.EmcSwizzleRank1Byte2 = 0x27043615,
|
||||
.EmcSwizzleRank1Byte3 = 0x72306145,
|
||||
.EmcDsrVttgenDrv = 0x0606003f,
|
||||
.EmcTxdsrvttgen = 0x00000000,
|
||||
.EmcBgbiasCtl0 = 0x00000000,
|
||||
.McEmemAdrCfg = 0x00000000,
|
||||
.McEmemAdrCfgDev0 = 0x00080303,
|
||||
.McEmemAdrCfgDev1 = 0x00080303,
|
||||
.McEmemAdrCfgBankMask0 = 0x00001248,
|
||||
.McEmemAdrCfgBankMask1 = 0x00002490,
|
||||
.McEmemAdrCfgBankMask2 = 0x00000920,
|
||||
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
|
||||
.McEmemCfg = 0x00000800,
|
||||
.McEmemArbCfg = 0x0e00000d,
|
||||
.McEmemArbOutstandingReq = 0x80000040,
|
||||
.McEmemArbTimingRcd = 0x00000005,
|
||||
.McEmemArbTimingRp = 0x00000006,
|
||||
.McEmemArbTimingRc = 0x00000016,
|
||||
.McEmemArbTimingRas = 0x0000000e,
|
||||
.McEmemArbTimingFaw = 0x00000011,
|
||||
.McEmemArbTimingRrd = 0x00000002,
|
||||
.McEmemArbTimingRap2Pre = 0x00000004,
|
||||
.McEmemArbTimingWap2Pre = 0x0000000e,
|
||||
.McEmemArbTimingR2R = 0x00000002,
|
||||
.McEmemArbTimingW2W = 0x00000002,
|
||||
.McEmemArbTimingR2W = 0x00000006,
|
||||
.McEmemArbTimingW2R = 0x00000009,
|
||||
.McEmemArbDaTurns = 0x09060202,
|
||||
.McEmemArbDaCovers = 0x001a1016,
|
||||
.McEmemArbMisc0 = 0x734e2a17,
|
||||
.McEmemArbMisc1 = 0x70000f02,
|
||||
.McEmemArbRing1Throttle = 0x001f0000,
|
||||
.McEmemArbOverride = 0x10000000,
|
||||
.McEmemArbOverride1 = 0x00000000,
|
||||
.McEmemArbRsv = 0xff00ff00,
|
||||
.McClkenOverride = 0x00000000,
|
||||
.McStatControl = 0x00000000,
|
||||
.McDisplaySnapRing = 0x00000003,
|
||||
.McVideoProtectBom = 0xfff00000,
|
||||
.McVideoProtectBomAdrHi = 0x00000000,
|
||||
.McVideoProtectSizeMb = 0x00000000,
|
||||
.McVideoProtectVprOverride = 0xe4bac743,
|
||||
.McVideoProtectVprOverride1 = 0x00000013,
|
||||
.McVideoProtectGpuOverride0 = 0x00000000,
|
||||
.McVideoProtectGpuOverride1 = 0x00000000,
|
||||
.McSecCarveoutBom = 0xfff00000,
|
||||
.McSecCarveoutAdrHi = 0x00000000,
|
||||
.McSecCarveoutSizeMb = 0x00000000,
|
||||
.McVideoProtectWriteAccess = 0x00000000,
|
||||
.McSecCarveoutProtectWriteAccess = 0x00000000,
|
||||
.EmcCaTrainingEnable = 0x00000000,
|
||||
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
|
||||
.EmcCaTrainingTimingCntl2 = 0x0000001f,
|
||||
.SwizzleRankByteEncode = 0x0000006f,
|
||||
.BootRomPatchControl = 0x00000000,
|
||||
.BootRomPatchData = 0x00000000,
|
||||
.McMtsCarveoutBom = 0xfff00000,
|
||||
.McMtsCarveoutAdrHi = 0x00000000,
|
||||
.McMtsCarveoutSizeMb = 0x00000000,
|
||||
.McMtsCarveoutRegCtrl = 0x00000000,
|
||||
},
|
||||
311
src/mainboard/google/nyan_big/bct/sdram-0100-204-4GB.inc
Normal file
311
src/mainboard/google/nyan_big/bct/sdram-0100-204-4GB.inc
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
{ /* generated from sdram-0100-204-4GB.cfg; do not edit. */
|
||||
.MemoryType = NvBootMemoryType_Ddr3,
|
||||
.PllMInputDivider = 0x00000001,
|
||||
.PllMFeedbackDivider = 0x00000022,
|
||||
.PllMStableTime = 0x0000012c,
|
||||
.PllMSetupControl = 0x00000000,
|
||||
.PllMSelectDiv2 = 0x00000000,
|
||||
.PllMPDLshiftPh45 = 0x00000001,
|
||||
.PllMPDLshiftPh90 = 0x00000001,
|
||||
.PllMPDLshiftPh135 = 0x00000001,
|
||||
.PllMKCP = 0x00000000,
|
||||
.PllMKVCO = 0x00000000,
|
||||
.EmcBctSpare0 = 0x00000000,
|
||||
.EmcBctSpare1 = 0x00000000,
|
||||
.EmcBctSpare2 = 0x00000000,
|
||||
.EmcBctSpare3 = 0x00000000,
|
||||
.EmcBctSpare4 = 0x00000000,
|
||||
.EmcBctSpare5 = 0x00000000,
|
||||
.EmcBctSpare6 = 0x00000000,
|
||||
.EmcBctSpare7 = 0x00000000,
|
||||
.EmcBctSpare8 = 0x00000000,
|
||||
.EmcBctSpare9 = 0x00000000,
|
||||
.EmcBctSpare10 = 0x00000000,
|
||||
.EmcBctSpare11 = 0x00000000,
|
||||
.EmcClockSource = 0x40000002,
|
||||
.EmcAutoCalInterval = 0x001fffff,
|
||||
.EmcAutoCalConfig = 0xa1430000,
|
||||
.EmcAutoCalConfig2 = 0x00000000,
|
||||
.EmcAutoCalConfig3 = 0x00000000,
|
||||
.EmcAutoCalWait = 0x00000190,
|
||||
.EmcAdrCfg = 0x00000001,
|
||||
.EmcPinProgramWait = 0x00000001,
|
||||
.EmcPinExtraWait = 0x00000000,
|
||||
.EmcTimingControlWait = 0x00000000,
|
||||
.EmcRc = 0x00000009,
|
||||
.EmcRfc = 0x00000047,
|
||||
.EmcRfcSlr = 0x00000000,
|
||||
.EmcRas = 0x00000007,
|
||||
.EmcRp = 0x00000002,
|
||||
.EmcR2r = 0x00000000,
|
||||
.EmcW2w = 0x00000000,
|
||||
.EmcR2w = 0x00000005,
|
||||
.EmcW2r = 0x0000000a,
|
||||
.EmcR2p = 0x00000003,
|
||||
.EmcW2p = 0x0000000b,
|
||||
.EmcRdRcd = 0x00000002,
|
||||
.EmcWrRcd = 0x00000002,
|
||||
.EmcRrd = 0x00000003,
|
||||
.EmcRext = 0x00000003,
|
||||
.EmcWext = 0x00000000,
|
||||
.EmcWdv = 0x00000005,
|
||||
.EmcWdvMask = 0x00000005,
|
||||
.EmcQUse = 0x00000006,
|
||||
.EmcQuseWidth = 0x00000002,
|
||||
.EmcIbdly = 0x00000000,
|
||||
.EmcEInput = 0x00000004,
|
||||
.EmcEInputDuration = 0x00000006,
|
||||
.EmcPutermExtra = 0x00010000,
|
||||
.EmcPutermWidth = 0x00000003,
|
||||
.EmcPutermAdj = 0x00000000,
|
||||
.EmcCdbCntl1 = 0x00000000,
|
||||
.EmcCdbCntl2 = 0x00000000,
|
||||
.EmcCdbCntl3 = 0x00000000,
|
||||
.EmcQRst = 0x00000003,
|
||||
.EmcQSafe = 0x0000000d,
|
||||
.EmcRdv = 0x0000000f,
|
||||
.EmcRdvMask = 0x00000011,
|
||||
.EmcQpop = 0x0000000a,
|
||||
.EmcCtt = 0x00000000,
|
||||
.EmcCttDuration = 0x00000003,
|
||||
.EmcRefresh = 0x00000607,
|
||||
.EmcBurstRefreshNum = 0x00000000,
|
||||
.EmcPreRefreshReqCnt = 0x00000181,
|
||||
.EmcPdEx2Wr = 0x00000002,
|
||||
.EmcPdEx2Rd = 0x00000002,
|
||||
.EmcPChg2Pden = 0x00000001,
|
||||
.EmcAct2Pden = 0x00000000,
|
||||
.EmcAr2Pden = 0x00000044,
|
||||
.EmcRw2Pden = 0x0000000f,
|
||||
.EmcTxsr = 0x0000004a,
|
||||
.EmcTxsrDll = 0x0000004a,
|
||||
.EmcTcke = 0x00000004,
|
||||
.EmcTckesr = 0x00000005,
|
||||
.EmcTpd = 0x00000004,
|
||||
.EmcTfaw = 0x00000007,
|
||||
.EmcTrpab = 0x00000000,
|
||||
.EmcTClkStable = 0x00000005,
|
||||
.EmcTClkStop = 0x00000005,
|
||||
.EmcTRefBw = 0x00000638,
|
||||
.EmcFbioCfg5 = 0x106aa298,
|
||||
.EmcFbioCfg6 = 0x00000000,
|
||||
.EmcFbioSpare = 0x00000000,
|
||||
.EmcCfgRsv = 0xff00ff00,
|
||||
.EmcMrs = 0x00001221,
|
||||
.EmcEmrs = 0x00100003,
|
||||
.EmcEmrs2 = 0x00200008,
|
||||
.EmcEmrs3 = 0x00300000,
|
||||
.EmcMrw1 = 0x00000000,
|
||||
.EmcMrw2 = 0x00000000,
|
||||
.EmcMrw3 = 0x00000000,
|
||||
.EmcMrw4 = 0x00000000,
|
||||
.EmcMrwExtra = 0x00000000,
|
||||
.EmcWarmBootMrwExtra = 0x00000000,
|
||||
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcMrwResetCommand = 0x00000000,
|
||||
.EmcMrwResetNInitWait = 0x00000000,
|
||||
.EmcMrsWaitCnt = 0x000c000c,
|
||||
.EmcMrsWaitCnt2 = 0x000c000c,
|
||||
.EmcCfg = 0x73240000,
|
||||
.EmcCfg2 = 0x0000088d,
|
||||
.EmcCfgPipe = 0x0000d2b3,
|
||||
.EmcDbg = 0x01000c00,
|
||||
.EmcCmdQ = 0x10004408,
|
||||
.EmcMc2EmcQ = 0x06000404,
|
||||
.EmcDynSelfRefControl = 0x80000d22,
|
||||
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
|
||||
.EmcCfgDigDll = 0x002c00a0,
|
||||
.EmcCfgDigDllPeriod = 0x00008000,
|
||||
.EmcDevSelect = 0x00000000,
|
||||
.EmcSelDpdCtrl = 0x00040008,
|
||||
.EmcDllXformDqs0 = 0x00064000,
|
||||
.EmcDllXformDqs1 = 0x00064000,
|
||||
.EmcDllXformDqs2 = 0x00064000,
|
||||
.EmcDllXformDqs3 = 0x00064000,
|
||||
.EmcDllXformDqs4 = 0x00064000,
|
||||
.EmcDllXformDqs5 = 0x00064000,
|
||||
.EmcDllXformDqs6 = 0x00064000,
|
||||
.EmcDllXformDqs7 = 0x00064000,
|
||||
.EmcDllXformDqs8 = 0x00064000,
|
||||
.EmcDllXformDqs9 = 0x00064000,
|
||||
.EmcDllXformDqs10 = 0x00064000,
|
||||
.EmcDllXformDqs11 = 0x00064000,
|
||||
.EmcDllXformDqs12 = 0x00064000,
|
||||
.EmcDllXformDqs13 = 0x00064000,
|
||||
.EmcDllXformDqs14 = 0x00064000,
|
||||
.EmcDllXformDqs15 = 0x00064000,
|
||||
.EmcDllXformQUse0 = 0x00000000,
|
||||
.EmcDllXformQUse1 = 0x00000000,
|
||||
.EmcDllXformQUse2 = 0x00000000,
|
||||
.EmcDllXformQUse3 = 0x00000000,
|
||||
.EmcDllXformQUse4 = 0x00000000,
|
||||
.EmcDllXformQUse5 = 0x00000000,
|
||||
.EmcDllXformQUse6 = 0x00000000,
|
||||
.EmcDllXformQUse7 = 0x00000000,
|
||||
.EmcDllXformAddr0 = 0x00000000,
|
||||
.EmcDllXformAddr1 = 0x00000000,
|
||||
.EmcDllXformAddr2 = 0x00004000,
|
||||
.EmcDllXformAddr3 = 0x00000000,
|
||||
.EmcDllXformAddr4 = 0x00000000,
|
||||
.EmcDllXformAddr5 = 0x00004000,
|
||||
.EmcDllXformQUse8 = 0x00000000,
|
||||
.EmcDllXformQUse9 = 0x00000000,
|
||||
.EmcDllXformQUse10 = 0x00000000,
|
||||
.EmcDllXformQUse11 = 0x00000000,
|
||||
.EmcDllXformQUse12 = 0x00000000,
|
||||
.EmcDllXformQUse13 = 0x00000000,
|
||||
.EmcDllXformQUse14 = 0x00000000,
|
||||
.EmcDllXformQUse15 = 0x00000000,
|
||||
.EmcDliTrimTxDqs0 = 0x00000000,
|
||||
.EmcDliTrimTxDqs1 = 0x00000000,
|
||||
.EmcDliTrimTxDqs2 = 0x00000000,
|
||||
.EmcDliTrimTxDqs3 = 0x00000000,
|
||||
.EmcDliTrimTxDqs4 = 0x00000000,
|
||||
.EmcDliTrimTxDqs5 = 0x00000000,
|
||||
.EmcDliTrimTxDqs6 = 0x00000000,
|
||||
.EmcDliTrimTxDqs7 = 0x00000000,
|
||||
.EmcDliTrimTxDqs8 = 0x00000000,
|
||||
.EmcDliTrimTxDqs9 = 0x00000000,
|
||||
.EmcDliTrimTxDqs10 = 0x00000000,
|
||||
.EmcDliTrimTxDqs11 = 0x00000000,
|
||||
.EmcDliTrimTxDqs12 = 0x00000000,
|
||||
.EmcDliTrimTxDqs13 = 0x00000000,
|
||||
.EmcDliTrimTxDqs14 = 0x00000000,
|
||||
.EmcDliTrimTxDqs15 = 0x00000000,
|
||||
.EmcDllXformDq0 = 0x00090000,
|
||||
.EmcDllXformDq1 = 0x00090000,
|
||||
.EmcDllXformDq2 = 0x00094000,
|
||||
.EmcDllXformDq3 = 0x00094000,
|
||||
.EmcDllXformDq4 = 0x00009400,
|
||||
.EmcDllXformDq5 = 0x00009000,
|
||||
.EmcDllXformDq6 = 0x00009000,
|
||||
.EmcDllXformDq7 = 0x00009000,
|
||||
.WarmBootWait = 0x00000002,
|
||||
.EmcCttTermCtrl = 0x00000802,
|
||||
.EmcOdtWrite = 0x00000000,
|
||||
.EmcOdtRead = 0x00000000,
|
||||
.EmcZcalInterval = 0x00020000,
|
||||
.EmcZcalWaitCnt = 0x00000042,
|
||||
.EmcZcalMrwCmd = 0x00000000,
|
||||
.EmcMrsResetDll = 0x00000000,
|
||||
.EmcZcalInitDev0 = 0x80000011,
|
||||
.EmcZcalInitDev1 = 0x40000011,
|
||||
.EmcZcalInitWait = 0x00000003,
|
||||
.EmcZcalWarmColdBootEnables = 0x00000003,
|
||||
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
|
||||
.EmcZqCalDdr3WarmBoot = 0x00000000,
|
||||
.EmcZcalWarmBootWait = 0x00000002,
|
||||
.EmcMrsWarmBootEnable = 0x00000001,
|
||||
.EmcMrsResetDllWait = 0x00000000,
|
||||
.EmcMrsExtra = 0x00001221,
|
||||
.EmcWarmBootMrsExtra = 0x00100003,
|
||||
.EmcEmrsDdr2DllEnable = 0x00000000,
|
||||
.EmcMrsDdr2DllReset = 0x00000000,
|
||||
.EmcEmrsDdr2OcdCalib = 0x00000000,
|
||||
.EmcDdr2Wait = 0x00000000,
|
||||
.EmcClkenOverride = 0x00000000,
|
||||
.McDisExtraSnapLevels = 0x00000000,
|
||||
.EmcExtraRefreshNum = 0x00000002,
|
||||
.EmcClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.McClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
|
||||
.PmcVddpSel = 0x00000002,
|
||||
.PmcVddpSelWait = 0x00000002,
|
||||
.PmcDdrPwr = 0x00000003,
|
||||
.PmcDdrCfg = 0x00002002,
|
||||
.PmcIoDpd3Req = 0x4fffffff,
|
||||
.PmcIoDpd3ReqWait = 0x00000000,
|
||||
.PmcRegShort = 0x00000000,
|
||||
.PmcNoIoPower = 0x00000000,
|
||||
.PmcPorDpdCtrlWait = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl = 0x10000280,
|
||||
.EmcXm2CmdPadCtrl2 = 0x770c0000,
|
||||
.EmcXm2CmdPadCtrl3 = 0x050c0000,
|
||||
.EmcXm2CmdPadCtrl4 = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl5 = 0x00111111,
|
||||
.EmcXm2DqsPadCtrl = 0x770c1414,
|
||||
.EmcXm2DqsPadCtrl2 = 0x0130b118,
|
||||
.EmcXm2DqsPadCtrl3 = 0x51451400,
|
||||
.EmcXm2DqsPadCtrl4 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl5 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl6 = 0x51451400,
|
||||
.EmcXm2DqPadCtrl = 0x770c2990,
|
||||
.EmcXm2DqPadCtrl2 = 0x00000000,
|
||||
.EmcXm2DqPadCtrl3 = 0x00000000,
|
||||
.EmcXm2ClkPadCtrl = 0x77ffc081,
|
||||
.EmcXm2ClkPadCtrl2 = 0x00000303,
|
||||
.EmcXm2CompPadCtrl = 0x81f1f108,
|
||||
.EmcXm2VttGenPadCtrl = 0x07070004,
|
||||
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
|
||||
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
|
||||
.EmcAcpdControl = 0x00000000,
|
||||
.EmcSwizzleRank0ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank0Byte0 = 0x25143067,
|
||||
.EmcSwizzleRank0Byte1 = 0x45367102,
|
||||
.EmcSwizzleRank0Byte2 = 0x47106253,
|
||||
.EmcSwizzleRank0Byte3 = 0x04362175,
|
||||
.EmcSwizzleRank1ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank1Byte0 = 0x71546032,
|
||||
.EmcSwizzleRank1Byte1 = 0x35104276,
|
||||
.EmcSwizzleRank1Byte2 = 0x27043615,
|
||||
.EmcSwizzleRank1Byte3 = 0x72306145,
|
||||
.EmcDsrVttgenDrv = 0x0000003f,
|
||||
.EmcTxdsrvttgen = 0x00000066,
|
||||
.EmcBgbiasCtl0 = 0x00000008,
|
||||
.McEmemAdrCfg = 0x00000001,
|
||||
.McEmemAdrCfgDev0 = 0x00080303,
|
||||
.McEmemAdrCfgDev1 = 0x00080303,
|
||||
.McEmemAdrCfgBankMask0 = 0x00001248,
|
||||
.McEmemAdrCfgBankMask1 = 0x00002490,
|
||||
.McEmemAdrCfgBankMask2 = 0x00000920,
|
||||
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
|
||||
.McEmemCfg = 0x00001000,
|
||||
.McEmemArbCfg = 0x01000003,
|
||||
.McEmemArbOutstandingReq = 0x80000040,
|
||||
.McEmemArbTimingRcd = 0x00000001,
|
||||
.McEmemArbTimingRp = 0x00000001,
|
||||
.McEmemArbTimingRc = 0x00000005,
|
||||
.McEmemArbTimingRas = 0x00000002,
|
||||
.McEmemArbTimingFaw = 0x00000004,
|
||||
.McEmemArbTimingRrd = 0x00000001,
|
||||
.McEmemArbTimingRap2Pre = 0x00000002,
|
||||
.McEmemArbTimingWap2Pre = 0x00000008,
|
||||
.McEmemArbTimingR2R = 0x00000003,
|
||||
.McEmemArbTimingW2W = 0x00000002,
|
||||
.McEmemArbTimingR2W = 0x00000004,
|
||||
.McEmemArbTimingW2R = 0x00000006,
|
||||
.McEmemArbDaTurns = 0x06040203,
|
||||
.McEmemArbDaCovers = 0x000a0405,
|
||||
.McEmemArbMisc0 = 0x74a40a06,
|
||||
.McEmemArbMisc1 = 0x70000f03,
|
||||
.McEmemArbRing1Throttle = 0x001f0000,
|
||||
.McEmemArbOverride = 0x10000000,
|
||||
.McEmemArbOverride1 = 0x00000000,
|
||||
.McEmemArbRsv = 0xff00ff00,
|
||||
.McClkenOverride = 0x00000000,
|
||||
.McStatControl = 0x00000000,
|
||||
.McDisplaySnapRing = 0x00000003,
|
||||
.McVideoProtectBom = 0xfff00000,
|
||||
.McVideoProtectBomAdrHi = 0x00000000,
|
||||
.McVideoProtectSizeMb = 0x00000000,
|
||||
.McVideoProtectVprOverride = 0xe4bac743,
|
||||
.McVideoProtectVprOverride1 = 0x00000013,
|
||||
.McVideoProtectGpuOverride0 = 0x00000000,
|
||||
.McVideoProtectGpuOverride1 = 0x00000000,
|
||||
.McSecCarveoutBom = 0xfff00000,
|
||||
.McSecCarveoutAdrHi = 0x00000000,
|
||||
.McSecCarveoutSizeMb = 0x00000000,
|
||||
.McVideoProtectWriteAccess = 0x00000000,
|
||||
.McSecCarveoutProtectWriteAccess = 0x00000000,
|
||||
.EmcCaTrainingEnable = 0x00000000,
|
||||
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
|
||||
.EmcCaTrainingTimingCntl2 = 0x0000001f,
|
||||
.SwizzleRankByteEncode = 0x0000006f,
|
||||
.BootRomPatchControl = 0x00000000,
|
||||
.BootRomPatchData = 0x00000000,
|
||||
.McMtsCarveoutBom = 0xfff00000,
|
||||
.McMtsCarveoutAdrHi = 0x00000000,
|
||||
.McMtsCarveoutSizeMb = 0x00000000,
|
||||
.McMtsCarveoutRegCtrl = 0x00000000,
|
||||
},
|
||||
311
src/mainboard/google/nyan_big/bct/sdram-0100-792-4GB.inc
Normal file
311
src/mainboard/google/nyan_big/bct/sdram-0100-792-4GB.inc
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */
|
||||
.MemoryType = NvBootMemoryType_Ddr3,
|
||||
.PllMInputDivider = 0x00000001,
|
||||
.PllMFeedbackDivider = 0x00000042,
|
||||
.PllMStableTime = 0x0000012c,
|
||||
.PllMSetupControl = 0x00000000,
|
||||
.PllMSelectDiv2 = 0x00000000,
|
||||
.PllMPDLshiftPh45 = 0x00000001,
|
||||
.PllMPDLshiftPh90 = 0x00000001,
|
||||
.PllMPDLshiftPh135 = 0x00000001,
|
||||
.PllMKCP = 0x00000000,
|
||||
.PllMKVCO = 0x00000000,
|
||||
.EmcBctSpare0 = 0x00000000,
|
||||
.EmcBctSpare1 = 0x00000000,
|
||||
.EmcBctSpare2 = 0x00000000,
|
||||
.EmcBctSpare3 = 0x00000000,
|
||||
.EmcBctSpare4 = 0x00000000,
|
||||
.EmcBctSpare5 = 0x00000000,
|
||||
.EmcBctSpare6 = 0x00000000,
|
||||
.EmcBctSpare7 = 0x00000000,
|
||||
.EmcBctSpare8 = 0x00000000,
|
||||
.EmcBctSpare9 = 0x00000000,
|
||||
.EmcBctSpare10 = 0x00000000,
|
||||
.EmcBctSpare11 = 0x00000000,
|
||||
.EmcClockSource = 0x80000000,
|
||||
.EmcAutoCalInterval = 0x001fffff,
|
||||
.EmcAutoCalConfig = 0xa1430000,
|
||||
.EmcAutoCalConfig2 = 0x00000000,
|
||||
.EmcAutoCalConfig3 = 0x00000000,
|
||||
.EmcAutoCalWait = 0x00000190,
|
||||
.EmcAdrCfg = 0x00000001,
|
||||
.EmcPinProgramWait = 0x00000001,
|
||||
.EmcPinExtraWait = 0x00000000,
|
||||
.EmcTimingControlWait = 0x00000000,
|
||||
.EmcRc = 0x00000025,
|
||||
.EmcRfc = 0x00000114,
|
||||
.EmcRfcSlr = 0x00000000,
|
||||
.EmcRas = 0x0000001a,
|
||||
.EmcRp = 0x00000007,
|
||||
.EmcR2r = 0x00000000,
|
||||
.EmcW2w = 0x00000000,
|
||||
.EmcR2w = 0x00000008,
|
||||
.EmcW2r = 0x0000000d,
|
||||
.EmcR2p = 0x00000004,
|
||||
.EmcW2p = 0x00000013,
|
||||
.EmcRdRcd = 0x00000009,
|
||||
.EmcWrRcd = 0x00000009,
|
||||
.EmcRrd = 0x00000003,
|
||||
.EmcRext = 0x00000002,
|
||||
.EmcWext = 0x00000000,
|
||||
.EmcWdv = 0x00000006,
|
||||
.EmcWdvMask = 0x00000006,
|
||||
.EmcQUse = 0x0000000b,
|
||||
.EmcQuseWidth = 0x00000002,
|
||||
.EmcIbdly = 0x00000000,
|
||||
.EmcEInput = 0x00000002,
|
||||
.EmcEInputDuration = 0x0000000d,
|
||||
.EmcPutermExtra = 0x00080000,
|
||||
.EmcPutermWidth = 0x00000004,
|
||||
.EmcPutermAdj = 0x00000000,
|
||||
.EmcCdbCntl1 = 0x00000000,
|
||||
.EmcCdbCntl2 = 0x00000000,
|
||||
.EmcCdbCntl3 = 0x00000000,
|
||||
.EmcQRst = 0x00000001,
|
||||
.EmcQSafe = 0x00000014,
|
||||
.EmcRdv = 0x00000018,
|
||||
.EmcRdvMask = 0x0000001a,
|
||||
.EmcQpop = 0x0000000f,
|
||||
.EmcCtt = 0x00000000,
|
||||
.EmcCttDuration = 0x00000004,
|
||||
.EmcRefresh = 0x000017e2,
|
||||
.EmcBurstRefreshNum = 0x00000000,
|
||||
.EmcPreRefreshReqCnt = 0x000005f8,
|
||||
.EmcPdEx2Wr = 0x00000003,
|
||||
.EmcPdEx2Rd = 0x00000011,
|
||||
.EmcPChg2Pden = 0x00000001,
|
||||
.EmcAct2Pden = 0x00000000,
|
||||
.EmcAr2Pden = 0x0000010d,
|
||||
.EmcRw2Pden = 0x00000018,
|
||||
.EmcTxsr = 0x0000011e,
|
||||
.EmcTxsrDll = 0x00000200,
|
||||
.EmcTcke = 0x00000005,
|
||||
.EmcTckesr = 0x00000006,
|
||||
.EmcTpd = 0x00000005,
|
||||
.EmcTfaw = 0x0000001d,
|
||||
.EmcTrpab = 0x00000000,
|
||||
.EmcTClkStable = 0x00000008,
|
||||
.EmcTClkStop = 0x00000008,
|
||||
.EmcTRefBw = 0x00001822,
|
||||
.EmcFbioCfg5 = 0x104ab098,
|
||||
.EmcFbioCfg6 = 0x00000000,
|
||||
.EmcFbioSpare = 0x00000000,
|
||||
.EmcCfgRsv = 0xff00ff00,
|
||||
.EmcMrs = 0x00000d71,
|
||||
.EmcEmrs = 0x00100002,
|
||||
.EmcEmrs2 = 0x00200018,
|
||||
.EmcEmrs3 = 0x00300000,
|
||||
.EmcMrw1 = 0x00000000,
|
||||
.EmcMrw2 = 0x00000000,
|
||||
.EmcMrw3 = 0x00000000,
|
||||
.EmcMrw4 = 0x00000000,
|
||||
.EmcMrwExtra = 0x00000000,
|
||||
.EmcWarmBootMrwExtra = 0x00000000,
|
||||
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcExtraModeRegWriteEnable = 0x00000000,
|
||||
.EmcMrwResetCommand = 0x00000000,
|
||||
.EmcMrwResetNInitWait = 0x00000000,
|
||||
.EmcMrsWaitCnt = 0x006f000c,
|
||||
.EmcMrsWaitCnt2 = 0x006f000c,
|
||||
.EmcCfg = 0x73300000,
|
||||
.EmcCfg2 = 0x0000089d,
|
||||
.EmcCfgPipe = 0x00004080,
|
||||
.EmcDbg = 0x01000c00,
|
||||
.EmcCmdQ = 0x10004408,
|
||||
.EmcMc2EmcQ = 0x06000404,
|
||||
.EmcDynSelfRefControl = 0x80003012,
|
||||
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
|
||||
.EmcCfgDigDll = 0xe00700b1,
|
||||
.EmcCfgDigDllPeriod = 0x00008000,
|
||||
.EmcDevSelect = 0x00000000,
|
||||
.EmcSelDpdCtrl = 0x00040000,
|
||||
.EmcDllXformDqs0 = 0x00000008,
|
||||
.EmcDllXformDqs1 = 0x00000008,
|
||||
.EmcDllXformDqs2 = 0x00000008,
|
||||
.EmcDllXformDqs3 = 0x00000008,
|
||||
.EmcDllXformDqs4 = 0x00000008,
|
||||
.EmcDllXformDqs5 = 0x00000008,
|
||||
.EmcDllXformDqs6 = 0x00000008,
|
||||
.EmcDllXformDqs7 = 0x00000008,
|
||||
.EmcDllXformDqs8 = 0x00000008,
|
||||
.EmcDllXformDqs9 = 0x00000008,
|
||||
.EmcDllXformDqs10 = 0x00000008,
|
||||
.EmcDllXformDqs11 = 0x00000008,
|
||||
.EmcDllXformDqs12 = 0x00000008,
|
||||
.EmcDllXformDqs13 = 0x00000008,
|
||||
.EmcDllXformDqs14 = 0x00000008,
|
||||
.EmcDllXformDqs15 = 0x00000008,
|
||||
.EmcDllXformQUse0 = 0x00000000,
|
||||
.EmcDllXformQUse1 = 0x00000000,
|
||||
.EmcDllXformQUse2 = 0x00000000,
|
||||
.EmcDllXformQUse3 = 0x00000000,
|
||||
.EmcDllXformQUse4 = 0x00000000,
|
||||
.EmcDllXformQUse5 = 0x00000000,
|
||||
.EmcDllXformQUse6 = 0x00000000,
|
||||
.EmcDllXformQUse7 = 0x00000000,
|
||||
.EmcDllXformAddr0 = 0x00034000,
|
||||
.EmcDllXformAddr1 = 0x00034000,
|
||||
.EmcDllXformAddr2 = 0x00000000,
|
||||
.EmcDllXformAddr3 = 0x00034000,
|
||||
.EmcDllXformAddr4 = 0x00034000,
|
||||
.EmcDllXformAddr5 = 0x00000000,
|
||||
.EmcDllXformQUse8 = 0x00000000,
|
||||
.EmcDllXformQUse9 = 0x00000000,
|
||||
.EmcDllXformQUse10 = 0x00000000,
|
||||
.EmcDllXformQUse11 = 0x00000000,
|
||||
.EmcDllXformQUse12 = 0x00000000,
|
||||
.EmcDllXformQUse13 = 0x00000000,
|
||||
.EmcDllXformQUse14 = 0x00000000,
|
||||
.EmcDllXformQUse15 = 0x00000000,
|
||||
.EmcDliTrimTxDqs0 = 0x00000008,
|
||||
.EmcDliTrimTxDqs1 = 0x00000008,
|
||||
.EmcDliTrimTxDqs2 = 0x00000005,
|
||||
.EmcDliTrimTxDqs3 = 0x00000009,
|
||||
.EmcDliTrimTxDqs4 = 0x00000009,
|
||||
.EmcDliTrimTxDqs5 = 0x00000007,
|
||||
.EmcDliTrimTxDqs6 = 0x00000009,
|
||||
.EmcDliTrimTxDqs7 = 0x00000008,
|
||||
.EmcDliTrimTxDqs8 = 0x00000008,
|
||||
.EmcDliTrimTxDqs9 = 0x00000008,
|
||||
.EmcDliTrimTxDqs10 = 0x00000005,
|
||||
.EmcDliTrimTxDqs11 = 0x00000009,
|
||||
.EmcDliTrimTxDqs12 = 0x00000009,
|
||||
.EmcDliTrimTxDqs13 = 0x00000007,
|
||||
.EmcDliTrimTxDqs14 = 0x00000009,
|
||||
.EmcDliTrimTxDqs15 = 0x00000008,
|
||||
.EmcDllXformDq0 = 0x0000000e,
|
||||
.EmcDllXformDq1 = 0x0000000e,
|
||||
.EmcDllXformDq2 = 0x0000000e,
|
||||
.EmcDllXformDq3 = 0x0000000e,
|
||||
.EmcDllXformDq4 = 0x0000000e,
|
||||
.EmcDllXformDq5 = 0x0000000e,
|
||||
.EmcDllXformDq6 = 0x0000000e,
|
||||
.EmcDllXformDq7 = 0x0000000e,
|
||||
.WarmBootWait = 0x00000002,
|
||||
.EmcCttTermCtrl = 0x00000802,
|
||||
.EmcOdtWrite = 0x00000000,
|
||||
.EmcOdtRead = 0x00000000,
|
||||
.EmcZcalInterval = 0x00020000,
|
||||
.EmcZcalWaitCnt = 0x00000042,
|
||||
.EmcZcalMrwCmd = 0x00000000,
|
||||
.EmcMrsResetDll = 0x00000000,
|
||||
.EmcZcalInitDev0 = 0x80000011,
|
||||
.EmcZcalInitDev1 = 0x40000011,
|
||||
.EmcZcalInitWait = 0x00000001,
|
||||
.EmcZcalWarmColdBootEnables = 0x00000003,
|
||||
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
|
||||
.EmcZqCalDdr3WarmBoot = 0x00000000,
|
||||
.EmcZcalWarmBootWait = 0x00000001,
|
||||
.EmcMrsWarmBootEnable = 0x00000001,
|
||||
.EmcMrsResetDllWait = 0x00000000,
|
||||
.EmcMrsExtra = 0x00000d71,
|
||||
.EmcWarmBootMrsExtra = 0x00100002,
|
||||
.EmcEmrsDdr2DllEnable = 0x00000000,
|
||||
.EmcMrsDdr2DllReset = 0x00000000,
|
||||
.EmcEmrsDdr2OcdCalib = 0x00000000,
|
||||
.EmcDdr2Wait = 0x00000000,
|
||||
.EmcClkenOverride = 0x00000000,
|
||||
.McDisExtraSnapLevels = 0x00000000,
|
||||
.EmcExtraRefreshNum = 0x00000002,
|
||||
.EmcClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.McClkenOverrideAllWarmBoot = 0x00000000,
|
||||
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
|
||||
.PmcVddpSel = 0x00000002,
|
||||
.PmcVddpSelWait = 0x00000002,
|
||||
.PmcDdrPwr = 0x00000003,
|
||||
.PmcDdrCfg = 0x00002002,
|
||||
.PmcIoDpd3Req = 0x4fffffff,
|
||||
.PmcIoDpd3ReqWait = 0x00000000,
|
||||
.PmcRegShort = 0x00000000,
|
||||
.PmcNoIoPower = 0x00000000,
|
||||
.PmcPorDpdCtrlWait = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl = 0x100002a0,
|
||||
.EmcXm2CmdPadCtrl2 = 0x770c0000,
|
||||
.EmcXm2CmdPadCtrl3 = 0x050c0000,
|
||||
.EmcXm2CmdPadCtrl4 = 0x00000000,
|
||||
.EmcXm2CmdPadCtrl5 = 0x00111111,
|
||||
.EmcXm2DqsPadCtrl = 0x770c1414,
|
||||
.EmcXm2DqsPadCtrl2 = 0x0120113d,
|
||||
.EmcXm2DqsPadCtrl3 = 0x61861820,
|
||||
.EmcXm2DqsPadCtrl4 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl5 = 0x00514514,
|
||||
.EmcXm2DqsPadCtrl6 = 0x61861800,
|
||||
.EmcXm2DqPadCtrl = 0x770c2990,
|
||||
.EmcXm2DqPadCtrl2 = 0x00000000,
|
||||
.EmcXm2DqPadCtrl3 = 0x00000000,
|
||||
.EmcXm2ClkPadCtrl = 0x77ffc085,
|
||||
.EmcXm2ClkPadCtrl2 = 0x00000101,
|
||||
.EmcXm2CompPadCtrl = 0x81f1f108,
|
||||
.EmcXm2VttGenPadCtrl = 0x07070004,
|
||||
.EmcXm2VttGenPadCtrl2 = 0x00000000,
|
||||
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
|
||||
.EmcAcpdControl = 0x00000000,
|
||||
.EmcSwizzleRank0ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank0Byte0 = 0x25143067,
|
||||
.EmcSwizzleRank0Byte1 = 0x45367102,
|
||||
.EmcSwizzleRank0Byte2 = 0x47106253,
|
||||
.EmcSwizzleRank0Byte3 = 0x04362175,
|
||||
.EmcSwizzleRank1ByteCfg = 0x00003120,
|
||||
.EmcSwizzleRank1Byte0 = 0x71546032,
|
||||
.EmcSwizzleRank1Byte1 = 0x35104276,
|
||||
.EmcSwizzleRank1Byte2 = 0x27043615,
|
||||
.EmcSwizzleRank1Byte3 = 0x72306145,
|
||||
.EmcDsrVttgenDrv = 0x0606003f,
|
||||
.EmcTxdsrvttgen = 0x00000000,
|
||||
.EmcBgbiasCtl0 = 0x00000000,
|
||||
.McEmemAdrCfg = 0x00000001,
|
||||
.McEmemAdrCfgDev0 = 0x00080303,
|
||||
.McEmemAdrCfgDev1 = 0x00080303,
|
||||
.McEmemAdrCfgBankMask0 = 0x00001248,
|
||||
.McEmemAdrCfgBankMask1 = 0x00002490,
|
||||
.McEmemAdrCfgBankMask2 = 0x00000920,
|
||||
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
|
||||
.McEmemCfg = 0x00001000,
|
||||
.McEmemArbCfg = 0x0e00000b,
|
||||
.McEmemArbOutstandingReq = 0x80000040,
|
||||
.McEmemArbTimingRcd = 0x00000004,
|
||||
.McEmemArbTimingRp = 0x00000004,
|
||||
.McEmemArbTimingRc = 0x00000013,
|
||||
.McEmemArbTimingRas = 0x0000000c,
|
||||
.McEmemArbTimingFaw = 0x0000000f,
|
||||
.McEmemArbTimingRrd = 0x00000002,
|
||||
.McEmemArbTimingRap2Pre = 0x00000003,
|
||||
.McEmemArbTimingWap2Pre = 0x0000000c,
|
||||
.McEmemArbTimingR2R = 0x00000002,
|
||||
.McEmemArbTimingW2W = 0x00000002,
|
||||
.McEmemArbTimingR2W = 0x00000006,
|
||||
.McEmemArbTimingW2R = 0x00000008,
|
||||
.McEmemArbDaTurns = 0x08060202,
|
||||
.McEmemArbDaCovers = 0x00150c13,
|
||||
.McEmemArbMisc0 = 0x746c2414,
|
||||
.McEmemArbMisc1 = 0x70000f02,
|
||||
.McEmemArbRing1Throttle = 0x001f0000,
|
||||
.McEmemArbOverride = 0x10000000,
|
||||
.McEmemArbOverride1 = 0x00000000,
|
||||
.McEmemArbRsv = 0xff00ff00,
|
||||
.McClkenOverride = 0x00000000,
|
||||
.McStatControl = 0x00000000,
|
||||
.McDisplaySnapRing = 0x00000003,
|
||||
.McVideoProtectBom = 0xfff00000,
|
||||
.McVideoProtectBomAdrHi = 0x00000000,
|
||||
.McVideoProtectSizeMb = 0x00000000,
|
||||
.McVideoProtectVprOverride = 0xe4bac743,
|
||||
.McVideoProtectVprOverride1 = 0x00000013,
|
||||
.McVideoProtectGpuOverride0 = 0x00000000,
|
||||
.McVideoProtectGpuOverride1 = 0x00000000,
|
||||
.McSecCarveoutBom = 0xfff00000,
|
||||
.McSecCarveoutAdrHi = 0x00000000,
|
||||
.McSecCarveoutSizeMb = 0x00000000,
|
||||
.McVideoProtectWriteAccess = 0x00000000,
|
||||
.McSecCarveoutProtectWriteAccess = 0x00000000,
|
||||
.EmcCaTrainingEnable = 0x00000000,
|
||||
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
|
||||
.EmcCaTrainingTimingCntl2 = 0x0000001f,
|
||||
.SwizzleRankByteEncode = 0x0000006f,
|
||||
.BootRomPatchControl = 0x00000000,
|
||||
.BootRomPatchData = 0x00000000,
|
||||
.McMtsCarveoutBom = 0xfff00000,
|
||||
.McMtsCarveoutAdrHi = 0x00000000,
|
||||
.McMtsCarveoutSizeMb = 0x00000000,
|
||||
.McMtsCarveoutRegCtrl = 0x00000000,
|
||||
},
|
||||
|
|
@ -1,346 +0,0 @@
|
|||
# Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command:
|
||||
# t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 4.90196
|
||||
# -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o big_0121_2GB_204Mhz.cfg
|
||||
# -b big_0121_204MHz_emc_reg.txt
|
||||
# Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 4.90 ns (204.00 MHz)
|
||||
# bkv file: big_0121_204MHz_emc_reg.txt
|
||||
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
|
||||
SDRAM[0].PllMInputDivider = 0x00000001;
|
||||
SDRAM[0].PllMFeedbackDivider = 0x00000022;
|
||||
SDRAM[0].PllMStableTime = 0x0000012c;
|
||||
SDRAM[0].PllMSetupControl = 0x00000000;
|
||||
SDRAM[0].PllMSelectDiv2 = 0x00000000;
|
||||
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
|
||||
SDRAM[0].PllMKCP = 0x00000000;
|
||||
SDRAM[0].PllMKVCO = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare0 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare1 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare2 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare3 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare4 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare5 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare6 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare7 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare8 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare9 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare10 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare11 = 0x00000000;
|
||||
SDRAM[0].EmcClockSource = 0x40000002;
|
||||
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
|
||||
SDRAM[0].EmcAutoCalConfig = 0xa1430000;
|
||||
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalWait = 0x00000190;
|
||||
SDRAM[0].EmcAdrCfg = 0x00000000;
|
||||
SDRAM[0].EmcPinProgramWait = 0x00000001;
|
||||
SDRAM[0].EmcPinExtraWait = 0x00000000;
|
||||
SDRAM[0].EmcTimingControlWait = 0x00000000;
|
||||
SDRAM[0].EmcRc = 0x00000009;
|
||||
SDRAM[0].EmcRfc = 0x00000035;
|
||||
SDRAM[0].EmcRfcSlr = 0x00000000;
|
||||
SDRAM[0].EmcRas = 0x00000007;
|
||||
SDRAM[0].EmcRp = 0x00000002;
|
||||
SDRAM[0].EmcR2r = 0x00000000;
|
||||
SDRAM[0].EmcW2w = 0x00000000;
|
||||
SDRAM[0].EmcR2w = 0x00000005;
|
||||
SDRAM[0].EmcW2r = 0x0000000a;
|
||||
SDRAM[0].EmcR2p = 0x00000003;
|
||||
SDRAM[0].EmcW2p = 0x0000000b;
|
||||
SDRAM[0].EmcRdRcd = 0x00000002;
|
||||
SDRAM[0].EmcWrRcd = 0x00000002;
|
||||
SDRAM[0].EmcRrd = 0x00000003;
|
||||
SDRAM[0].EmcRext = 0x00000003;
|
||||
SDRAM[0].EmcWext = 0x00000000;
|
||||
SDRAM[0].EmcWdv = 0x00000005;
|
||||
SDRAM[0].EmcWdvMask = 0x00000005;
|
||||
SDRAM[0].EmcQUse = 0x00000006;
|
||||
SDRAM[0].EmcQuseWidth = 0x00000002;
|
||||
SDRAM[0].EmcIbdly = 0x00000000;
|
||||
SDRAM[0].EmcEInput = 0x00000004;
|
||||
SDRAM[0].EmcEInputDuration = 0x00000006;
|
||||
SDRAM[0].EmcPutermExtra = 0x00010000;
|
||||
SDRAM[0].EmcPutermWidth = 0x00000003;
|
||||
SDRAM[0].EmcPutermAdj = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl1 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl2 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl3 = 0x00000000;
|
||||
SDRAM[0].EmcQRst = 0x00000003;
|
||||
SDRAM[0].EmcQSafe = 0x0000000d;
|
||||
SDRAM[0].EmcRdv = 0x0000000f;
|
||||
SDRAM[0].EmcRdvMask = 0x00000011;
|
||||
SDRAM[0].EmcQpop = 0x0000000a;
|
||||
SDRAM[0].EmcCtt = 0x00000000;
|
||||
SDRAM[0].EmcCttDuration = 0x00000003;
|
||||
SDRAM[0].EmcRefresh = 0x00000607;
|
||||
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
|
||||
SDRAM[0].EmcPreRefreshReqCnt = 0x00000181;
|
||||
SDRAM[0].EmcPdEx2Wr = 0x00000002;
|
||||
SDRAM[0].EmcPdEx2Rd = 0x00000002;
|
||||
SDRAM[0].EmcPChg2Pden = 0x00000001;
|
||||
SDRAM[0].EmcAct2Pden = 0x00000000;
|
||||
SDRAM[0].EmcAr2Pden = 0x00000032;
|
||||
SDRAM[0].EmcRw2Pden = 0x0000000f;
|
||||
SDRAM[0].EmcTxsr = 0x00000038;
|
||||
SDRAM[0].EmcTxsrDll = 0x00000038;
|
||||
SDRAM[0].EmcTcke = 0x00000004;
|
||||
SDRAM[0].EmcTckesr = 0x00000005;
|
||||
SDRAM[0].EmcTpd = 0x00000004;
|
||||
SDRAM[0].EmcTfaw = 0x00000007;
|
||||
SDRAM[0].EmcTrpab = 0x00000000;
|
||||
SDRAM[0].EmcTClkStable = 0x00000005;
|
||||
SDRAM[0].EmcTClkStop = 0x00000005;
|
||||
SDRAM[0].EmcTRefBw = 0x00000638;
|
||||
SDRAM[0].EmcFbioCfg5 = 0x106aa298;
|
||||
SDRAM[0].EmcFbioCfg6 = 0x00000000;
|
||||
SDRAM[0].EmcFbioSpare = 0x00000000;
|
||||
SDRAM[0].EmcCfgRsv = 0xff00ff00;
|
||||
SDRAM[0].EmcMrs = 0x80001221;
|
||||
SDRAM[0].EmcEmrs = 0x80100003;
|
||||
SDRAM[0].EmcEmrs2 = 0x80200008;
|
||||
SDRAM[0].EmcEmrs3 = 0x80300000;
|
||||
SDRAM[0].EmcMrw1 = 0x00000000;
|
||||
SDRAM[0].EmcMrw2 = 0x00000000;
|
||||
SDRAM[0].EmcMrw3 = 0x00000000;
|
||||
SDRAM[0].EmcMrw4 = 0x00000000;
|
||||
SDRAM[0].EmcMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetCommand = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsWaitCnt = 0x000c000c;
|
||||
SDRAM[0].EmcMrsWaitCnt2 = 0x000c000c;
|
||||
SDRAM[0].EmcCfg = 0x73240000;
|
||||
SDRAM[0].EmcCfg2 = 0x0000088d;
|
||||
SDRAM[0].EmcCfgPipe = 0x0000d2b3;
|
||||
SDRAM[0].EmcDbg = 0x01000c00;
|
||||
SDRAM[0].EmcCmdQ = 0x10004408;
|
||||
SDRAM[0].EmcMc2EmcQ = 0x06000404;
|
||||
SDRAM[0].EmcDynSelfRefControl = 0x80000d22;
|
||||
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
|
||||
SDRAM[0].EmcCfgDigDll = 0x002c00a0;
|
||||
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
|
||||
SDRAM[0].EmcDevSelect = 0x00000002;
|
||||
SDRAM[0].EmcSelDpdCtrl = 0x00040008;
|
||||
SDRAM[0].EmcDllXformDqs0 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs1 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs2 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs3 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs4 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs5 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs6 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs7 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs8 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs9 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs10 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs11 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs12 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs13 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs14 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformDqs15 = 0x00064000;
|
||||
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr0 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr1 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr2 = 0x00004000;
|
||||
SDRAM[0].EmcDllXformAddr3 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr4 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr5 = 0x00004000;
|
||||
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformDq0 = 0x00090000;
|
||||
SDRAM[0].EmcDllXformDq1 = 0x00090000;
|
||||
SDRAM[0].EmcDllXformDq2 = 0x00094000;
|
||||
SDRAM[0].EmcDllXformDq3 = 0x00094000;
|
||||
SDRAM[0].EmcDllXformDq4 = 0x00009400;
|
||||
SDRAM[0].EmcDllXformDq5 = 0x00009000;
|
||||
SDRAM[0].EmcDllXformDq6 = 0x00009000;
|
||||
SDRAM[0].EmcDllXformDq7 = 0x00009000;
|
||||
SDRAM[0].WarmBootWait = 0x00000002;
|
||||
SDRAM[0].EmcCttTermCtrl = 0x00000802;
|
||||
SDRAM[0].EmcOdtWrite = 0x00000000;
|
||||
SDRAM[0].EmcOdtRead = 0x00000000;
|
||||
SDRAM[0].EmcZcalInterval = 0x00020000;
|
||||
SDRAM[0].EmcZcalWaitCnt = 0x00000042;
|
||||
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
|
||||
SDRAM[0].EmcMrsResetDll = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
|
||||
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitWait = 0x00000003;
|
||||
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
|
||||
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
|
||||
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcZcalWarmBootWait = 0x00000002;
|
||||
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
|
||||
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsExtra = 0x80001221;
|
||||
SDRAM[0].EmcWarmBootMrsExtra = 0x80100003;
|
||||
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
|
||||
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
|
||||
SDRAM[0].EmcDdr2Wait = 0x00000000;
|
||||
SDRAM[0].EmcClkenOverride = 0x00000000;
|
||||
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
|
||||
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
|
||||
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
|
||||
SDRAM[0].PmcVddpSel = 0x00000002;
|
||||
SDRAM[0].PmcVddpSelWait = 0x00000002;
|
||||
SDRAM[0].PmcDdrPwr = 0x00000003;
|
||||
SDRAM[0].PmcDdrCfg = 0x00002002;
|
||||
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
|
||||
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
|
||||
SDRAM[0].PmcRegShort = 0x00000000;
|
||||
SDRAM[0].PmcNoIoPower = 0x00000000;
|
||||
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl = 0x10000280;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0130b118;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x51451400;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x51451400;
|
||||
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
|
||||
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
|
||||
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc081;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
|
||||
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x0000003f;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
|
||||
SDRAM[0].EmcAcpdControl = 0x00000000;
|
||||
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
|
||||
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
|
||||
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
|
||||
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
|
||||
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
|
||||
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
|
||||
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
|
||||
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
|
||||
SDRAM[0].EmcDsrVttgenDrv = 0x0000003f;
|
||||
SDRAM[0].EmcTxdsrvttgen = 0x00000066;
|
||||
SDRAM[0].EmcBgbiasCtl0 = 0x00000008;
|
||||
SDRAM[0].McEmemAdrCfg = 0x00000000;
|
||||
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
|
||||
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
|
||||
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
|
||||
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
|
||||
SDRAM[0].McEmemCfg = 0x00000800;
|
||||
SDRAM[0].McEmemArbCfg = 0x01000003;
|
||||
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
|
||||
SDRAM[0].McEmemArbTimingRcd = 0x00000001;
|
||||
SDRAM[0].McEmemArbTimingRp = 0x00000001;
|
||||
SDRAM[0].McEmemArbTimingRc = 0x00000005;
|
||||
SDRAM[0].McEmemArbTimingRas = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingFaw = 0x00000004;
|
||||
SDRAM[0].McEmemArbTimingRrd = 0x00000001;
|
||||
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingWap2Pre = 0x00000008;
|
||||
SDRAM[0].McEmemArbTimingR2R = 0x00000003;
|
||||
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingR2W = 0x00000004;
|
||||
SDRAM[0].McEmemArbTimingW2R = 0x00000006;
|
||||
SDRAM[0].McEmemArbDaTurns = 0x06040203;
|
||||
SDRAM[0].McEmemArbDaCovers = 0x000a0405;
|
||||
SDRAM[0].McEmemArbMisc0 = 0x73840a06;
|
||||
SDRAM[0].McEmemArbMisc1 = 0x70000f03;
|
||||
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
|
||||
SDRAM[0].McEmemArbOverride = 0x10000000;
|
||||
SDRAM[0].McEmemArbOverride1 = 0x00000000;
|
||||
SDRAM[0].McEmemArbRsv = 0xff00ff00;
|
||||
SDRAM[0].McClkenOverride = 0x00000000;
|
||||
SDRAM[0].McStatControl = 0x00000000;
|
||||
SDRAM[0].McDisplaySnapRing = 0x00000003;
|
||||
SDRAM[0].McVideoProtectBom = 0xfff00000;
|
||||
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
|
||||
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
|
||||
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
|
||||
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
|
||||
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
|
||||
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
|
||||
SDRAM[0].BootRomPatchControl = 0x00000000;
|
||||
SDRAM[0].BootRomPatchData = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
|
||||
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000001;
|
||||
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x00000062;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00ff006d;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00ff006d;
|
||||
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x00ff003c;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00ff00af;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00ff004f;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00ff00af;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00ff004f;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x004e0049;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00ff0080;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00ff0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00ff0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080057;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x000000ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00ff0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00ff0063;
|
||||
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00ff0036;
|
||||
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00ff0024;
|
||||
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x00ff006b;
|
||||
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x000000ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000050;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00ff00ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000050;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00ff00ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510050;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00ff00ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00ff00ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00ff00c6;
|
||||
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x00ff006d;
|
||||
|
|
@ -1,347 +0,0 @@
|
|||
#Hynix 2GB
|
||||
# Do not edit. Generated by t124_emc_reg_tool5.0.14.exe V5.0.14. Command:
|
||||
# t124_emc_reg_tool5.0.14.exe -i extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par 1.26262
|
||||
# -is_mid_package 1 -dram_board_cfg 10 -round_trip_dly_ps 624 -o big_0121_2GB_792Mhz.cfg
|
||||
# -b big_0121_792MHz_emc_reg.txt
|
||||
# Parameter file: extras\param_files\ddr3_256Mx16x4_H5TC4G63AFR_PBA_01212014.par, tck = 1.26 ns (792.00 MHz)
|
||||
# bkv file: big_0121_792MHz_emc_reg.txt
|
||||
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
|
||||
SDRAM[0].PllMInputDivider = 0x00000001;
|
||||
SDRAM[0].PllMFeedbackDivider = 0x00000042;
|
||||
SDRAM[0].PllMStableTime = 0x0000012c;
|
||||
SDRAM[0].PllMSetupControl = 0x00000000;
|
||||
SDRAM[0].PllMSelectDiv2 = 0x00000000;
|
||||
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
|
||||
SDRAM[0].PllMKCP = 0x00000000;
|
||||
SDRAM[0].PllMKVCO = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare0 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare1 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare2 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare3 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare4 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare5 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare6 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare7 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare8 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare9 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare10 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare11 = 0x00000000;
|
||||
SDRAM[0].EmcClockSource = 0x80000000;
|
||||
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
|
||||
SDRAM[0].EmcAutoCalConfig = 0xa1430000;
|
||||
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalWait = 0x00000190;
|
||||
SDRAM[0].EmcAdrCfg = 0x00000000;
|
||||
SDRAM[0].EmcPinProgramWait = 0x00000001;
|
||||
SDRAM[0].EmcPinExtraWait = 0x00000000;
|
||||
SDRAM[0].EmcTimingControlWait = 0x00000000;
|
||||
SDRAM[0].EmcRc = 0x00000025;
|
||||
SDRAM[0].EmcRfc = 0x000000cc;
|
||||
SDRAM[0].EmcRfcSlr = 0x00000000;
|
||||
SDRAM[0].EmcRas = 0x0000001a;
|
||||
SDRAM[0].EmcRp = 0x00000009;
|
||||
SDRAM[0].EmcR2r = 0x00000000;
|
||||
SDRAM[0].EmcW2w = 0x00000000;
|
||||
SDRAM[0].EmcR2w = 0x00000008;
|
||||
SDRAM[0].EmcW2r = 0x0000000d;
|
||||
SDRAM[0].EmcR2p = 0x00000004;
|
||||
SDRAM[0].EmcW2p = 0x00000013;
|
||||
SDRAM[0].EmcRdRcd = 0x00000009;
|
||||
SDRAM[0].EmcWrRcd = 0x00000009;
|
||||
SDRAM[0].EmcRrd = 0x00000003;
|
||||
SDRAM[0].EmcRext = 0x00000002;
|
||||
SDRAM[0].EmcWext = 0x00000000;
|
||||
SDRAM[0].EmcWdv = 0x00000006;
|
||||
SDRAM[0].EmcWdvMask = 0x00000006;
|
||||
SDRAM[0].EmcQUse = 0x0000000b;
|
||||
SDRAM[0].EmcQuseWidth = 0x00000002;
|
||||
SDRAM[0].EmcIbdly = 0x00000000;
|
||||
SDRAM[0].EmcEInput = 0x00000002;
|
||||
SDRAM[0].EmcEInputDuration = 0x0000000d;
|
||||
SDRAM[0].EmcPutermExtra = 0x00080000;
|
||||
SDRAM[0].EmcPutermWidth = 0x00000004;
|
||||
SDRAM[0].EmcPutermAdj = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl1 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl2 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl3 = 0x00000000;
|
||||
SDRAM[0].EmcQRst = 0x00000001;
|
||||
SDRAM[0].EmcQSafe = 0x00000014;
|
||||
SDRAM[0].EmcRdv = 0x00000018;
|
||||
SDRAM[0].EmcRdvMask = 0x0000001a;
|
||||
SDRAM[0].EmcQpop = 0x0000000f;
|
||||
SDRAM[0].EmcCtt = 0x00000000;
|
||||
SDRAM[0].EmcCttDuration = 0x00000004;
|
||||
SDRAM[0].EmcRefresh = 0x000017e2;
|
||||
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
|
||||
SDRAM[0].EmcPreRefreshReqCnt = 0x000005f8;
|
||||
SDRAM[0].EmcPdEx2Wr = 0x00000003;
|
||||
SDRAM[0].EmcPdEx2Rd = 0x00000011;
|
||||
SDRAM[0].EmcPChg2Pden = 0x00000001;
|
||||
SDRAM[0].EmcAct2Pden = 0x00000000;
|
||||
SDRAM[0].EmcAr2Pden = 0x000000c6;
|
||||
SDRAM[0].EmcRw2Pden = 0x00000018;
|
||||
SDRAM[0].EmcTxsr = 0x000000d6;
|
||||
SDRAM[0].EmcTxsrDll = 0x00000200;
|
||||
SDRAM[0].EmcTcke = 0x00000005;
|
||||
SDRAM[0].EmcTckesr = 0x00000006;
|
||||
SDRAM[0].EmcTpd = 0x00000005;
|
||||
SDRAM[0].EmcTfaw = 0x0000001d;
|
||||
SDRAM[0].EmcTrpab = 0x00000000;
|
||||
SDRAM[0].EmcTClkStable = 0x00000008;
|
||||
SDRAM[0].EmcTClkStop = 0x00000008;
|
||||
SDRAM[0].EmcTRefBw = 0x00001822;
|
||||
SDRAM[0].EmcFbioCfg5 = 0x104ab098;
|
||||
SDRAM[0].EmcFbioCfg6 = 0x00000000;
|
||||
SDRAM[0].EmcFbioSpare = 0x00000000;
|
||||
SDRAM[0].EmcCfgRsv = 0xff00ff00;
|
||||
SDRAM[0].EmcMrs = 0x80000d71;
|
||||
SDRAM[0].EmcEmrs = 0x80100002;
|
||||
SDRAM[0].EmcEmrs2 = 0x80200018;
|
||||
SDRAM[0].EmcEmrs3 = 0x80300000;
|
||||
SDRAM[0].EmcMrw1 = 0x00000000;
|
||||
SDRAM[0].EmcMrw2 = 0x00000000;
|
||||
SDRAM[0].EmcMrw3 = 0x00000000;
|
||||
SDRAM[0].EmcMrw4 = 0x00000000;
|
||||
SDRAM[0].EmcMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetCommand = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsWaitCnt = 0x00f8000c;
|
||||
SDRAM[0].EmcMrsWaitCnt2 = 0x00f8000c;
|
||||
SDRAM[0].EmcCfg = 0x73300000;
|
||||
SDRAM[0].EmcCfg2 = 0x0000089d;
|
||||
SDRAM[0].EmcCfgPipe = 0x00004080;
|
||||
SDRAM[0].EmcDbg = 0x01000c00;
|
||||
SDRAM[0].EmcCmdQ = 0x10004408;
|
||||
SDRAM[0].EmcMc2EmcQ = 0x06000404;
|
||||
SDRAM[0].EmcDynSelfRefControl = 0x80003012;
|
||||
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
|
||||
SDRAM[0].EmcCfgDigDll = 0xe00700b1;
|
||||
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
|
||||
SDRAM[0].EmcDevSelect = 0x00000002;
|
||||
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
|
||||
SDRAM[0].EmcDllXformDqs0 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs1 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs2 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs3 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs4 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs5 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs6 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs7 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs8 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs9 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs10 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs11 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs12 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs13 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs14 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDqs15 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr0 = 0x00034000;
|
||||
SDRAM[0].EmcDllXformAddr1 = 0x00034000;
|
||||
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr3 = 0x00034000;
|
||||
SDRAM[0].EmcDllXformAddr4 = 0x00034000;
|
||||
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000008;
|
||||
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000008;
|
||||
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000005;
|
||||
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000007;
|
||||
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000008;
|
||||
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000008;
|
||||
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000008;
|
||||
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000005;
|
||||
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000007;
|
||||
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000009;
|
||||
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000008;
|
||||
SDRAM[0].EmcDllXformDq0 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq1 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq2 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq3 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq4 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq5 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq6 = 0x0000000e;
|
||||
SDRAM[0].EmcDllXformDq7 = 0x0000000e;
|
||||
SDRAM[0].WarmBootWait = 0x00000002;
|
||||
SDRAM[0].EmcCttTermCtrl = 0x00000802;
|
||||
SDRAM[0].EmcOdtWrite = 0x00000000;
|
||||
SDRAM[0].EmcOdtRead = 0x00000000;
|
||||
SDRAM[0].EmcZcalInterval = 0x00020000;
|
||||
SDRAM[0].EmcZcalWaitCnt = 0x00000042;
|
||||
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
|
||||
SDRAM[0].EmcMrsResetDll = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
|
||||
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitWait = 0x00000001;
|
||||
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
|
||||
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
|
||||
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
|
||||
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
|
||||
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsExtra = 0x80000d71;
|
||||
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
|
||||
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
|
||||
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
|
||||
SDRAM[0].EmcDdr2Wait = 0x00000000;
|
||||
SDRAM[0].EmcClkenOverride = 0x00000000;
|
||||
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
|
||||
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
|
||||
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
|
||||
SDRAM[0].PmcVddpSel = 0x00000002;
|
||||
SDRAM[0].PmcVddpSelWait = 0x00000002;
|
||||
SDRAM[0].PmcDdrPwr = 0x00000003;
|
||||
SDRAM[0].PmcDdrCfg = 0x00002002;
|
||||
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
|
||||
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
|
||||
SDRAM[0].PmcRegShort = 0x00000000;
|
||||
SDRAM[0].PmcNoIoPower = 0x00000000;
|
||||
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0120113d;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
|
||||
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
|
||||
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
|
||||
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000101;
|
||||
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
|
||||
SDRAM[0].EmcAcpdControl = 0x00000000;
|
||||
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
|
||||
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
|
||||
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
|
||||
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
|
||||
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
|
||||
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
|
||||
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
|
||||
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
|
||||
SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
|
||||
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
|
||||
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
|
||||
SDRAM[0].McEmemAdrCfg = 0x00000000;
|
||||
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
|
||||
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
|
||||
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
|
||||
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
|
||||
SDRAM[0].McEmemCfg = 0x00000800;
|
||||
SDRAM[0].McEmemArbCfg = 0x0e00000b;
|
||||
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
|
||||
SDRAM[0].McEmemArbTimingRcd = 0x00000004;
|
||||
SDRAM[0].McEmemArbTimingRp = 0x00000005;
|
||||
SDRAM[0].McEmemArbTimingRc = 0x00000013;
|
||||
SDRAM[0].McEmemArbTimingRas = 0x0000000c;
|
||||
SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
|
||||
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
|
||||
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
|
||||
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingR2W = 0x00000006;
|
||||
SDRAM[0].McEmemArbTimingW2R = 0x00000008;
|
||||
SDRAM[0].McEmemArbDaTurns = 0x08060202;
|
||||
SDRAM[0].McEmemArbDaCovers = 0x00160d13;
|
||||
SDRAM[0].McEmemArbMisc0 = 0x734c2414;
|
||||
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
|
||||
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
|
||||
SDRAM[0].McEmemArbOverride = 0x10000000;
|
||||
SDRAM[0].McEmemArbOverride1 = 0x00000000;
|
||||
SDRAM[0].McEmemArbRsv = 0xff00ff00;
|
||||
SDRAM[0].McClkenOverride = 0x00000000;
|
||||
SDRAM[0].McStatControl = 0x00000000;
|
||||
SDRAM[0].McDisplaySnapRing = 0x00000003;
|
||||
SDRAM[0].McVideoProtectBom = 0xfff00000;
|
||||
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
|
||||
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
|
||||
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
|
||||
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
|
||||
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
|
||||
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
|
||||
SDRAM[0].BootRomPatchControl = 0x00000000;
|
||||
SDRAM[0].BootRomPatchData = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
|
||||
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
|
||||
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
|
||||
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
|
||||
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
|
||||
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
|
||||
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
|
||||
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
|
||||
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
|
||||
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
|
||||
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
|
||||
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;
|
||||
|
|
@ -1,346 +0,0 @@
|
|||
# CFG Version 11
|
||||
# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
|
||||
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
|
||||
# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
|
||||
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
|
||||
# bkv file: PM358/PM358_924MHz_emc_reg.txt
|
||||
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
|
||||
SDRAM[0].PllMInputDivider = 0x00000001;
|
||||
SDRAM[0].PllMFeedbackDivider = 0x0000004d;
|
||||
SDRAM[0].PllMStableTime = 0x0000012c;
|
||||
SDRAM[0].PllMSetupControl = 0x00000000;
|
||||
SDRAM[0].PllMSelectDiv2 = 0x00000000;
|
||||
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
|
||||
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
|
||||
SDRAM[0].PllMKCP = 0x00000000;
|
||||
SDRAM[0].PllMKVCO = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare0 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare1 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare2 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare3 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare4 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare5 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare6 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare7 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare8 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare9 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare10 = 0x00000000;
|
||||
SDRAM[0].EmcBctSpare11 = 0x00000000;
|
||||
SDRAM[0].EmcClockSource = 0x80000000;
|
||||
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
|
||||
SDRAM[0].EmcAutoCalConfig = 0xa1430404;
|
||||
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
|
||||
SDRAM[0].EmcAutoCalWait = 0x00000190;
|
||||
SDRAM[0].EmcAdrCfg = 0x00000000;
|
||||
SDRAM[0].EmcPinProgramWait = 0x00000001;
|
||||
SDRAM[0].EmcPinExtraWait = 0x00000000;
|
||||
SDRAM[0].EmcTimingControlWait = 0x00000000;
|
||||
SDRAM[0].EmcRc = 0x0000002b;
|
||||
SDRAM[0].EmcRfc = 0x000000ef;
|
||||
SDRAM[0].EmcRfcSlr = 0x00000000;
|
||||
SDRAM[0].EmcRas = 0x0000001e;
|
||||
SDRAM[0].EmcRp = 0x0000000b;
|
||||
SDRAM[0].EmcR2r = 0x00000000;
|
||||
SDRAM[0].EmcW2w = 0x00000000;
|
||||
SDRAM[0].EmcR2w = 0x00000008;
|
||||
SDRAM[0].EmcW2r = 0x0000000f;
|
||||
SDRAM[0].EmcR2p = 0x00000005;
|
||||
SDRAM[0].EmcW2p = 0x00000016;
|
||||
SDRAM[0].EmcRdRcd = 0x0000000b;
|
||||
SDRAM[0].EmcWrRcd = 0x0000000b;
|
||||
SDRAM[0].EmcRrd = 0x00000004;
|
||||
SDRAM[0].EmcRext = 0x00000002;
|
||||
SDRAM[0].EmcWext = 0x00000000;
|
||||
SDRAM[0].EmcWdv = 0x00000006;
|
||||
SDRAM[0].EmcWdvMask = 0x00000006;
|
||||
SDRAM[0].EmcQUse = 0x0000000c;
|
||||
SDRAM[0].EmcQuseWidth = 0x00000002;
|
||||
SDRAM[0].EmcIbdly = 0x00000000;
|
||||
SDRAM[0].EmcEInput = 0x00000002;
|
||||
SDRAM[0].EmcEInputDuration = 0x0000000e;
|
||||
SDRAM[0].EmcPutermExtra = 0x000a0000;
|
||||
SDRAM[0].EmcPutermWidth = 0x00000004;
|
||||
SDRAM[0].EmcPutermAdj = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl1 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl2 = 0x00000000;
|
||||
SDRAM[0].EmcCdbCntl3 = 0x00000000;
|
||||
SDRAM[0].EmcQRst = 0x00000001;
|
||||
SDRAM[0].EmcQSafe = 0x00000015;
|
||||
SDRAM[0].EmcRdv = 0x0000001b;
|
||||
SDRAM[0].EmcRdvMask = 0x0000001d;
|
||||
SDRAM[0].EmcQpop = 0x00000010;
|
||||
SDRAM[0].EmcCtt = 0x00000000;
|
||||
SDRAM[0].EmcCttDuration = 0x00000004;
|
||||
SDRAM[0].EmcRefresh = 0x00001be9;
|
||||
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
|
||||
SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
|
||||
SDRAM[0].EmcPdEx2Wr = 0x00000004;
|
||||
SDRAM[0].EmcPdEx2Rd = 0x00000015;
|
||||
SDRAM[0].EmcPChg2Pden = 0x00000001;
|
||||
SDRAM[0].EmcAct2Pden = 0x00000000;
|
||||
SDRAM[0].EmcAr2Pden = 0x000000e6;
|
||||
SDRAM[0].EmcRw2Pden = 0x0000001b;
|
||||
SDRAM[0].EmcTxsr = 0x000000fa;
|
||||
SDRAM[0].EmcTxsrDll = 0x00000200;
|
||||
SDRAM[0].EmcTcke = 0x00000006;
|
||||
SDRAM[0].EmcTckesr = 0x00000007;
|
||||
SDRAM[0].EmcTpd = 0x00000006;
|
||||
SDRAM[0].EmcTfaw = 0x00000022;
|
||||
SDRAM[0].EmcTrpab = 0x00000000;
|
||||
SDRAM[0].EmcTClkStable = 0x0000000a;
|
||||
SDRAM[0].EmcTClkStop = 0x0000000a;
|
||||
SDRAM[0].EmcTRefBw = 0x00001c29;
|
||||
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
|
||||
SDRAM[0].EmcFbioCfg6 = 0x00000002;
|
||||
SDRAM[0].EmcFbioSpare = 0x00000000;
|
||||
SDRAM[0].EmcCfgRsv = 0xff00ff00;
|
||||
SDRAM[0].EmcMrs = 0x80000f15;
|
||||
SDRAM[0].EmcEmrs = 0x80100002;
|
||||
SDRAM[0].EmcEmrs2 = 0x80200020;
|
||||
SDRAM[0].EmcEmrs3 = 0x80300000;
|
||||
SDRAM[0].EmcMrw1 = 0x00000000;
|
||||
SDRAM[0].EmcMrw2 = 0x00000000;
|
||||
SDRAM[0].EmcMrw3 = 0x00000000;
|
||||
SDRAM[0].EmcMrw4 = 0x00000000;
|
||||
SDRAM[0].EmcMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
|
||||
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetCommand = 0x00000000;
|
||||
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
|
||||
SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
|
||||
SDRAM[0].EmcCfg = 0x73300000;
|
||||
SDRAM[0].EmcCfg2 = 0x000008a5;
|
||||
SDRAM[0].EmcCfgPipe = 0x00000000;
|
||||
SDRAM[0].EmcDbg = 0x01000c00;
|
||||
SDRAM[0].EmcCmdQ = 0x10004408;
|
||||
SDRAM[0].EmcMc2EmcQ = 0x06000404;
|
||||
SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
|
||||
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
|
||||
SDRAM[0].EmcCfgDigDll = 0xe00401b1;
|
||||
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
|
||||
SDRAM[0].EmcDevSelect = 0x00000002;
|
||||
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
|
||||
SDRAM[0].EmcDllXformDqs0 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs1 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs2 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs3 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs4 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs5 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs6 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs7 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs8 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs9 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs10 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs11 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs12 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs13 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs14 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformDqs15 = 0x00000005;
|
||||
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
|
||||
SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
|
||||
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
|
||||
SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
|
||||
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
|
||||
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
|
||||
SDRAM[0].EmcDllXformDq0 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq1 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq2 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq3 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq4 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq5 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq6 = 0x00000006;
|
||||
SDRAM[0].EmcDllXformDq7 = 0x00000006;
|
||||
SDRAM[0].WarmBootWait = 0x00000002;
|
||||
SDRAM[0].EmcCttTermCtrl = 0x00000802;
|
||||
SDRAM[0].EmcOdtWrite = 0x00000000;
|
||||
SDRAM[0].EmcOdtRead = 0x00000000;
|
||||
SDRAM[0].EmcZcalInterval = 0x00020000;
|
||||
SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
|
||||
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
|
||||
SDRAM[0].EmcMrsResetDll = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
|
||||
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
|
||||
SDRAM[0].EmcZcalInitWait = 0x00000001;
|
||||
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
|
||||
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
|
||||
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
|
||||
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
|
||||
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
|
||||
SDRAM[0].EmcMrsExtra = 0x80000f15;
|
||||
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
|
||||
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
|
||||
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
|
||||
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
|
||||
SDRAM[0].EmcDdr2Wait = 0x00000000;
|
||||
SDRAM[0].EmcClkenOverride = 0x00000000;
|
||||
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
|
||||
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
|
||||
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
|
||||
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
|
||||
SDRAM[0].PmcVddpSel = 0x00000002;
|
||||
SDRAM[0].PmcVddpSelWait = 0x00000002;
|
||||
SDRAM[0].PmcDdrPwr = 0x00000003;
|
||||
SDRAM[0].PmcDdrCfg = 0x00002002;
|
||||
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
|
||||
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
|
||||
SDRAM[0].PmcRegShort = 0x00000000;
|
||||
SDRAM[0].PmcNoIoPower = 0x00000000;
|
||||
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
|
||||
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
|
||||
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
|
||||
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
|
||||
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
|
||||
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
|
||||
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
|
||||
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
|
||||
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
|
||||
SDRAM[0].EmcAcpdControl = 0x00000000;
|
||||
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
|
||||
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
|
||||
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
|
||||
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
|
||||
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
|
||||
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
|
||||
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
|
||||
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
|
||||
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
|
||||
SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
|
||||
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
|
||||
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
|
||||
SDRAM[0].McEmemAdrCfg = 0x00000000;
|
||||
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
|
||||
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
|
||||
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
|
||||
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
|
||||
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
|
||||
SDRAM[0].McEmemCfg = 0x00000800;
|
||||
SDRAM[0].McEmemArbCfg = 0x0e00000d;
|
||||
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
|
||||
SDRAM[0].McEmemArbTimingRcd = 0x00000005;
|
||||
SDRAM[0].McEmemArbTimingRp = 0x00000006;
|
||||
SDRAM[0].McEmemArbTimingRc = 0x00000016;
|
||||
SDRAM[0].McEmemArbTimingRas = 0x0000000e;
|
||||
SDRAM[0].McEmemArbTimingFaw = 0x00000011;
|
||||
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
|
||||
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
|
||||
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
|
||||
SDRAM[0].McEmemArbTimingR2W = 0x00000006;
|
||||
SDRAM[0].McEmemArbTimingW2R = 0x00000009;
|
||||
SDRAM[0].McEmemArbDaTurns = 0x09060202;
|
||||
SDRAM[0].McEmemArbDaCovers = 0x001a1016;
|
||||
SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
|
||||
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
|
||||
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
|
||||
SDRAM[0].McEmemArbOverride = 0x10000000;
|
||||
SDRAM[0].McEmemArbOverride1 = 0x00000000;
|
||||
SDRAM[0].McEmemArbRsv = 0xff00ff00;
|
||||
SDRAM[0].McClkenOverride = 0x00000000;
|
||||
SDRAM[0].McStatControl = 0x00000000;
|
||||
SDRAM[0].McDisplaySnapRing = 0x00000003;
|
||||
SDRAM[0].McVideoProtectBom = 0xfff00000;
|
||||
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
|
||||
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
|
||||
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
|
||||
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
|
||||
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
|
||||
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
|
||||
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
|
||||
SDRAM[0].BootRomPatchControl = 0x00000000;
|
||||
SDRAM[0].BootRomPatchData = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
|
||||
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
|
||||
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
|
||||
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
|
||||
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
|
||||
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
|
||||
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
|
||||
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
|
||||
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
|
||||
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
|
||||
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
|
||||
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
|
||||
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
|
||||
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
|
||||
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
|
||||
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
|
||||
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
|
||||
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;
|
||||
|
|
@ -25,6 +25,7 @@
|
|||
#include <cbfs.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include "sdram_configs.h"
|
||||
#include "soc/nvidia/tegra124/chip.h"
|
||||
#include "soc/nvidia/tegra124/sdram.h"
|
||||
#include <soc/display.h>
|
||||
|
|
@ -81,6 +82,8 @@ static void __attribute__((noinline)) romstage(void)
|
|||
console_init();
|
||||
exception_init();
|
||||
|
||||
sdram_init(get_sdram_config());
|
||||
|
||||
/* used for MMU and CBMEM setup */
|
||||
dram_size_mb = sdram_size_mb();
|
||||
|
||||
|
|
|
|||
62
src/mainboard/google/nyan_big/sdram_configs.c
Normal file
62
src/mainboard/google/nyan_big/sdram_configs.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <soc/nvidia/tegra124/sdram.h>
|
||||
#include "sdram_configs.h"
|
||||
|
||||
/*
|
||||
* Note for board bring up, we've temporarily filled SDRAM table with
|
||||
* 0001-204-2GB configuration (except the 0100-204-4GB entry).
|
||||
*/
|
||||
static struct sdram_params sdram_configs[] = {
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0100-204-4GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
#include "bct/sdram-0001-204-2GB.inc"
|
||||
};
|
||||
|
||||
const struct sdram_params *get_sdram_config()
|
||||
{
|
||||
uint32_t ramcode = sdram_get_ram_code();
|
||||
/*
|
||||
* If we need to apply some special hacks to RAMCODE mapping (ex, by
|
||||
* board_id), do that now.
|
||||
*/
|
||||
|
||||
printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
|
||||
if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
|
||||
sdram_configs[ramcode].AhbArbitrationXbarCtrlMemInitDone == 0) {
|
||||
die("Invalid RAMCODE.");
|
||||
}
|
||||
|
||||
return &sdram_configs[ramcode];
|
||||
}
|
||||
28
src/mainboard/google/nyan_big/sdram_configs.h
Normal file
28
src/mainboard/google/nyan_big/sdram_configs.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__
|
||||
#define __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__
|
||||
|
||||
#include <soc/nvidia/tegra124/sdram_param.h>
|
||||
|
||||
/* Loads SDRAM configurations for current system. */
|
||||
const struct sdram_params *get_sdram_config(void);
|
||||
|
||||
#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue