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broadwell: Clean up the bootblock code

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- Use the PCI device ID macros for device addressing
- Use the IO map defines from broadwell/iomap.h
- Clean up some macro defines that were renamed
- Clean up comments

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I2c1e0bc397f6a58fb51406835a9aa37f1c049b0a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 11:25:14 -07:00 • committed by chrome-internal-fetch
commit ba0206ab76
4 changed files with 23 additions and 37 deletions
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1
src/soc/intel/broadwell/bootblock/Makefile.inc Normal file
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@ -0,0 +1 @@
chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc

14
src/soc/intel/broadwell/bootblock/cpu.c
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@ -23,23 +23,15 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"
#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
#else
#error "CPU must be paired with Intel LynxPoint southbridge"
#endif
#include <broadwell/rcba.h>
#include <broadwell/msr.h>
static void set_var_mtrr(
unsigned reg, unsigned base, unsigned size, unsigned type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
@ -55,7 +47,7 @@ static void enable_rom_caching(void)
disable_cache();
/* Why only top 4MiB ? */
set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */

36
src/soc/intel/broadwell/bootblock/pch.c
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@ -19,17 +19,21 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
#include "pch.h"
#include <broadwell/iomap.h>
#include <broadwell/lpc.h>
#include <broadwell/pci_devs.h>
#include <broadwell/rcba.h>
#include <broadwell/spi.h>
static void store_initial_timestamp(void)
{
/* On Cougar Point we have two 32bit scratchpad registers available:
/* Two 32bit scratchpad registers available:
* D0:F0 0xdc (SKPAD)
* D31:F2 0xd0 (SATA SP)
*/
tsc_t tsc = rdtsc();
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
pci_write_config32(SA_DEV_ROOT, 0xdc, tsc.lo);
pci_write_config32(PCH_DEV_SATA, 0xd0, tsc.hi);
}
/*
@ -37,23 +41,16 @@ static void store_initial_timestamp(void)
*/
static void enable_spi_prefetch(void)
{
u8 reg8;
device_t dev;
dev = PCI_DEV(0, 0x1f, 0);
reg8 = pci_read_config8(dev, 0xdc);
u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, 0xdc, reg8);
pci_write_config8(PCH_DEV_LPC, 0xdc, reg8);
}
static void map_rcba(void)
{
device_t dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1);
}
static void enable_port80_on_lpc(void)
@ -71,18 +68,18 @@ static void set_spi_speed(void)
u8 ssfc;
/* Observe SPI Descriptor Component Section 0 */
SPIBAR32(FDOC) = 0x1000;
SPIBAR32(SPIBAR_FDOC) = 0x1000;
/* Extract the Write/Erase SPI Frequency from descriptor */
fdod = SPIBAR32(FDOD);
fdod = SPIBAR32(SPIBAR_FDOD);
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
ssfc = SPIBAR8(SSFC + 2);
ssfc = SPIBAR8(SPIBAR_SSFC + 2);
ssfc &= ~7;
ssfc |= fdod;
SPIBAR8(SSFC + 2) = ssfc;
SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
}
static void bootblock_southbridge_init(void)
@ -94,7 +91,4 @@ static void bootblock_southbridge_init(void)
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
}

9
src/soc/intel/broadwell/bootblock/systemagent.c
View file

@ -18,9 +18,8 @@
*/
#include <arch/io.h>
/* Just re-define this instead of including haswell.h. It blows up romcc. */
#define PCIEXBAR 0x60
#include <broadwell/pci_devs.h>
#include <broadwell/systemagent.h>
static void bootblock_northbridge_init(void)
{
@ -39,7 +38,7 @@ static void bootblock_northbridge_init(void)
* 4GiB.
*/
reg = 0;
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
}