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rambi: fix write-protect gpio reading at romstage

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On rambi there is an external 10K pull up while the hardware
resets GPIO_SUS[06]'s config to 20K pull down. These pulls
are fighting creating a voltage that when read as a digital
value is incorrect. Rectify this by disabling the intnernal
pull down.

BUG=chrome-os-partner:25641
BRANCH=baytrail
TEST=Built and booted. crossystem wpsw_boot is now correct.

Change-Id: I5f52c639e209ee75a41da8bd6ab4d1a9ae8fce16
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185741
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This commit is contained in:
Aaron Durbin 2014-02-10 16:36:01 -06:00 • committed by chrome-internal-fetch
commit c64627689b
1 changed files with 11 additions and 0 deletions
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11
src/mainboard/google/rambi/chromeos.c
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@ -109,6 +109,17 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
/*
* The vboot loader queries this function in romstage. The GPIOs have
* not been set up yet as that configuration is done in ramstage. The
* hardware defaults to an input but there is a 20K pulldown. Externally
* there is a 10K pullup. Disable the internal pull in romstage so that
* there isn't any ambiguity in the reading.
*/
#if defined(__PRE_RAM__)
ssus_disable_internal_pull(WP_STATUS_PAD);
#endif
/* WP is enabled when the pin is reading high. */
return ssus_get_gpio(WP_STATUS_PAD);
}