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broadwell: ACPI: Remove special handling of LPT-LP chipset

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Since the broadwell code only supports the "low power" variant
there is no need to check for it in the ACPI code.

BUG=chrome-os-partner:28234
TEST=None

Change-Id: I5347750cd627bcb4e4f5fce587df931725f417df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-05-01 09:27:39 -07:00 • committed by chrome-internal-fetch
commit 2c54df159b
3 changed files with 22 additions and 60 deletions
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13
src/soc/intel/broadwell/acpi/hda.asl
View file

@ -25,16 +25,5 @@
Device (HDEF)
{
Name (_ADR, 0x001b0000)
Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
Method (_PRW, 0) { // Power Resources for Wake
If (\ISLP ()) {
Return (PRWL)
} Else {
Return (PRWH)
}
}
Name (_PRW, Package () { 0x6d, 3 })
}

12
src/soc/intel/broadwell/acpi/pch.asl
View file

@ -22,16 +22,6 @@
Scope(\)
{
// Return TRUE if chipset is LynxPoint-LP
Method (ISLP, 0, NotSerialized)
{
If (LEqual (\_SB.PCI0.LPCB.DIDH, 0x9c)) {
Return (1)
} else {
Return (0)
}
}
// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
@ -82,7 +72,7 @@ Scope(\)
}
// High Definition Audio (Azalia) 0:1b.0
#include "audio.asl"
#include "hda.asl"
// PCI Express Ports 0:1c.x
#include "pcie.asl"

55
src/soc/intel/broadwell/acpi/xhci.asl
View file

@ -242,26 +242,22 @@ Device (XHCI)
Store (0, ^D0D3)
}
If (\ISLP ()) {
// Clear PCI 0xB0[14:13]
Store (0, ^MB13)
Store (0, ^MB14)
// Clear PCI 0xB0[14:13]
Store (0, ^MB13)
Store (0, ^MB14)
// Clear MMIO 0x816C[14,2]
Store (0, CLK0)
Store (0, CLK1)
}
// Clear MMIO 0x816C[14,2]
Store (0, CLK0)
Store (0, CLK1)
// Set MMIO 0x8154[31]
Store (1, CLK2)
If (\ISLP ()) {
// Handle per-port reset if needed
LPS0 ()
// Handle per-port reset if needed
LPS0 ()
// Set MMIO 0x80e0[15]
Store (1, AX15)
}
// Set MMIO 0x80e0[15]
Store (1, AX15)
Return ()
}
@ -301,23 +297,19 @@ Device (XHCI)
Store (0, ^D0D3)
}
If (\ISLP ()) {
// Set PCI 0xB0[14:13]
Store (1, ^MB13)
Store (1, ^MB14)
// Set PCI 0xB0[14:13]
Store (1, ^MB13)
Store (1, ^MB14)
// Set MMIO 0x816C[14,2]
Store (1, CLK0)
Store (1, CLK1)
}
// Set MMIO 0x816C[14,2]
Store (1, CLK0)
Store (1, CLK1)
// Clear MMIO 0x8154[31]
Store (0, CLK2)
If (\ISLP ()) {
// Clear MMIO 0x80e0[15]
Store (0, AX15)
}
// Clear MMIO 0x80e0[15]
Store (0, AX15)
// Put device in D3
Store (3, ^D0D3)
@ -325,16 +317,7 @@ Device (XHCI)
Return ()
}
Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H
Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP
Method (_PRW, 0) { // Power Resources for Wake
If (\ISLP ()) {
Return (PRWL)
} Else {
Return (PRWH)
}
}
Name (_PRW, Package(){ 0x6d, 3 })
// Leave USB ports on for to allow Wake from USB