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baytrail: lock down spi controller according to mainboard

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A mainboard_get_spi_config() is introduced to provide the
configuration details for locking down the SPI controller.
Honor those settings and lock down the SPI controller
in finalize_chipset().

BUG=chrome-os-partner:24624
BRANCH=baytrail
TEST=Built and booted with accompanying mainboard change.
     Noted SPI controller was locked down. Also confirmed
     event log entries were present for shutdowns and suspends.

Change-Id: Ie3f746ec1051bd46836992640f68dcc52753b1a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185631
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2014-02-09 16:00:53 -06:00 • committed by chrome-internal-fetch
commit 696ece68cb
2 changed files with 51 additions and 0 deletions
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32
src/soc/intel/baytrail/baytrail/spi.h
View file

@ -20,7 +20,25 @@
#ifndef _BAYTRAIL_SPI_H_
#define _BAYTRAIL_SPI_H_
#include <stdint.h>
/* These registers live behind SPI_BASE_ADDRESS. */
#define HSFSTS 0x04
# define FLOCKDN (0x1 << 15)
#define PREOP 0x94
#define OPTYPE 0x96
#define OPMENU0 0x98
#define OPMENU1 0x9c
#define LVSCC 0xc4
# define VCL (0x1 << 23)
# define EO(x) (((x) & 0xff) << 8)
# define WG_1_BYTE (0x0 << 2)
# define WG_64_BYTE (0x1 << 2)
# define BES_256_BYTE (0x0 << 0)
# define BES_4_KB (0x1 << 0)
# define BES_8_KB (0x2 << 0)
# define BES_64_KB (0x3 << 0)
#define UVSCC 0xc8
#define SCS 0xf8
# define SMIWPEN (0x1 << 7)
#define BCR 0xfc
@ -32,5 +50,19 @@
# define BCR_LE (0x1 << 1)
# define BCR_WPD (0x1 << 0)
/*
* SPI lockdown configuration.
*/
struct spi_config {
uint16_t preop;
uint16_t optype;
uint32_t opmenu[2];
uint32_t lvscc;
uint32_t uvscc;
};
/* Return 0 on success < 0 on failure. */
int mainboard_get_spi_config(struct spi_config *cfg);
#endif /* _BAYTRAIL_SPI_H_ */

19
src/soc/intel/baytrail/southcluster.c
View file

@ -423,12 +423,19 @@ static const struct pci_driver southcluster __pci_driver = {
.device = LPC_DEVID,
};
int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
{
return -1;
}
static void finalize_chipset(void *unused)
{
const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
const unsigned long gcs = RCBA_BASE_ADDRESS + GCS;
const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2;
const unsigned long etr = PMC_BASE_ADDRESS + ETR;
const unsigned long spi = SPI_BASE_ADDRESS;
struct spi_config cfg;
/* Set the lock enable on the BIOS control register. */
write32(bcr, read32(bcr) | BCR_LE);
@ -442,6 +449,18 @@ static void finalize_chipset(void *unused)
/* Set the CF9 lock. */
write32(etr, read32(etr) | CF9LOCK);
if (mainboard_get_spi_config(&cfg) < 0) {
printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
} else {
write16(spi + PREOP, cfg.preop);
write16(spi + OPTYPE, cfg.optype);
write32(spi + OPMENU0, cfg.opmenu[0]);
write32(spi + OPMENU1, cfg.opmenu[1]);
write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
write32(spi + UVSCC, cfg.uvscc);
write32(spi + LVSCC, cfg.lvscc | VCL);
}
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);
}