tegra124: more display PLL setup and clock hardcode removal.
Set up two new PLLs in the early clock code. Clear reset and enable clocks using the standrd function called from mainboard_init. Remove more hardcodes from display startup. This should be the end of moving clock code around. Next step is to remove all the display programming hardcodes for front porch, back porch, etc. and use the settings from the coreboot device tree. BUG=None TEST=Build, boot, see graphics BRANCH=None Change-Id: I324e57f665bbd11c1d09fb4b9ec14646d0785e5f Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/175732 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Ronald G. Minnich
chrome-internal-fetch
parent
32dd9947a6
commit
80402876b5
5 changed files with 34 additions and 98 deletions
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@ -54,8 +54,10 @@ static void set_clock_sources(void)
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CLK_DIVIDER(TEGRA_PLLP_KHZ, 408000),
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&clk_rst->clk_src_host1x);
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/* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */
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clock_configure_source(disp1, PLLC, 600000);
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/* DISP1 doesn't support a divisor. Use PLLD2_OUT0 which runs at 570MHz. */
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clrsetbits_le32(&clk_rst->clk_src_disp1,
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CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
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5 /*PLLD2_OUT0 */ << CLK_SOURCE_SHIFT);
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}
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static void setup_pinmux(void)
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@ -207,7 +209,7 @@ static void mainboard_init(device_t dev)
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CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
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CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
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CLK_V_I2C4,
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CLK_W_DVFS, 0);
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CLK_W_DVFS, CLK_X_DPAUX | CLK_X_SOR0);
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usb_setup_utmip1();
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/* USB2 is the camera, we don't need it in firmware */
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@ -269,11 +269,13 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
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u32 _rsv31; /* 0x554 */
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u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */
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u32 spare_reg0; /* _SPARE_REG0, 0x55c */
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u32 _rsv32[12]; /* 0x560-58c */
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u32 _rsv32[4]; /* 0x560-0x56c */
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u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
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u32 _rsv32_1[7]; /* 0x574-58c */
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u32 plldp_base; /* _PLLDP_BASE, 0x590 */
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u32 plldp_misc; /* _PLLDP_MISC, 0x594 */
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u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
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u32 _rsrv321[25];
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u32 _rsrv32_2[25];
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u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */
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u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */
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u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */
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@ -89,6 +89,7 @@ struct {
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struct pllpad_dividers plld; /* target: 925 MHz */
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struct pllu_dividers pllu; /* target; 960 MHz */
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struct pllcx_dividers plldp; /* target; 270 MHz */
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struct pllcx_dividers plld2; /* target; 570 MHz */
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} static const osc_table[16] = {
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[OSC_FREQ_OSC12]{
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.khz = 12000,
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@ -98,6 +99,7 @@ struct {
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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.plldp = {.n = 90, .m = 1, .p = 3}, /* 270 MHz */
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.plld2 = {.n = 95, .m = 1, .p = 1}, /* 570 MHz */
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},
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[OSC_FREQ_OSC13]{
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.khz = 13000,
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@ -107,6 +109,7 @@ struct {
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.plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12},
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12},
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.plldp = {.n = 83, .m = 1, .p = 3}, /* 269.75 MHz */
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.plld2 = {.n = 88, .m = 1, .p = 1}, /* 572 MHz */
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},
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[OSC_FREQ_OSC16P8]{
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.khz = 16800,
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@ -115,7 +118,8 @@ struct {
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.pllc = {.n = 250, .m = 7, .p = 0},
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.plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8},
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.plldp = {.n = 67, .m = 1, .p = 3}, /* 268 MHz */
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.plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */
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.plld2 = {.n = 68, .m = 1, .p = 1}, /* 571.2 MHz */
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},
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[OSC_FREQ_OSC19P2]{
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.khz = 19200,
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@ -124,7 +128,8 @@ struct {
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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.plldp = {.n = 57, .m = 1, .p = 3}, /* 270.75 MHz */
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.plldp = {.n = 56, .m = 1, .p = 3}, /* 270.75 MHz */
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.plld2 = {.n = 59, .m = 1, .p = 1}, /* 570 MHz */
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},
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[OSC_FREQ_OSC26]{
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.khz = 26000,
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@ -133,7 +138,8 @@ struct {
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
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.plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12},
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.pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8},
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.plldp = {.n = 41, .m = 1, .p = 3}, /* 266.50 MHz */
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.plldp = {.n = 83, .m = 2, .p = 3}, /* 266.50 MHz */
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.plld2 = {.n = 88, .m = 2, .p = 1}, /* 570 MHz */
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},
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[OSC_FREQ_OSC38P4]{
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.khz = 38400,
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@ -142,7 +148,8 @@ struct {
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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.plldp = {.n = 28, .m = 1, .p = 3}, /* 266 MHz */
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.plldp = {.n = 56, .m = 2, .p = 3}, /* 268 MHz */
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.plld2 = {.n = 59, .m = 2, .p = 1}, /* 566 MHz */
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},
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[OSC_FREQ_OSC48]{
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.khz = 48000,
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@ -151,7 +158,8 @@ struct {
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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.plldp = {.n = 22, .m = 1, .p = 3}, /* 264 MHz */
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.plldp = {.n = 90, .m = 4, .p = 3}, /* 264 MHz */
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.plld2 = {.n = 95, .m = 4, .p = 1}, /* 570 MHz */
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},
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};
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@ -213,6 +221,7 @@ void sor_clock_stop(void)
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void sor_clock_start(void)
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{
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/* uses PLLP, has a non-standard bit layout. */
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setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0);
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}
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@ -267,7 +276,7 @@ static void init_utmip_pll(void)
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* need to set in here, but it makes sense just to restrict all the
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* special bits to this one function.
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*/
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void graphics_clock(void)
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static void graphics_pll(void)
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{
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int osc = clock_get_osc_bits();
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u32 *cfg = &clk_rst->plldp_ss_cfg;
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@ -287,6 +296,13 @@ void graphics_clock(void)
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/* leave dither and undoc bits set, release clamp */
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scfg = (1<<28) | (1<<24);
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writel(scfg, cfg);
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/* a few more undocumented bits. Sorry. */
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writel(0x13400000, &clk_rst->plld2_ss_cfg); // undocumented
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init_pll(&clk_rst->plld2_base, &clk_rst->plld2_misc, osc_table[osc].plld2);
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writel(0x13800000, &clk_rst->plld2_ss_cfg); // undocumented
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udelay(10); // wait for plld2 ready
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}
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/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
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@ -405,6 +421,7 @@ void clock_init(void)
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init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
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init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
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init_utmip_pll();
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graphics_pll();
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val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
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writel(val, &clk_rst->clk_sys_rate);
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@ -50,9 +50,7 @@ int dpaux_read(u32 addr, u32 size, u8 * data);
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void init_dca_regs(void)
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{
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// u32 val;
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printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
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printk(BIOS_SPEW, "%s: entry\n", __func__);
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#if 1
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#define DCA_WRITE(reg, val) \
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@ -346,23 +344,9 @@ void init_dca_regs(void)
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void init_sor_regs(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
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printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
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#define SWR_SOR0_RST (1 << 22)
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#define CLK_ENB_SOR0 SWR_SOR0_RST
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// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 1)
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// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 0)
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// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_SOR0, 1)
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// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, 0) //0x60006414
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setbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Set Reset
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clrbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Clear Reset
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setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_SOR0); // Set Enable
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WRITEL(0x0, (void *)(0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = PLLP
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//WRITEL(0xc000c000, (0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = CLK_M
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#if 1
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#define SOR_WRITE(reg, val) \
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{ \
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@ -508,19 +492,8 @@ void init_sor_regs(void)
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void init_dpaux_regs(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
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// u32 val;
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printk(BIOS_SPEW, "JZ: %s: entry\n", __func__);
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#define SWR_DPAUX_RST (1 << 21)
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#define CLK_ENB_DPAUX SWR_DPAUX_RST
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// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 1)
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// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 0)
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// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_DPAUX, 1)
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setbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Set Reset
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clrbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Clear Reset
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setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_DPAUX); // Set Enable
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printk(BIOS_SPEW, "%s: entry\n", __func__);
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#if 1
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#define DPAUX_WRITE(reg, val) \
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@ -614,30 +587,8 @@ static void dp_io_set_dpd(u32 power_down)
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void dp_io_powerup(void)
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{
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//E_DPD = PMC.dpd2_status[25]
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//PDBG = SOR_NV_PDISP_SOR_PLL2_0.AUX6(1) | SEQ.POWERDOWN_MACRO(1) &
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//SOR_NV_PDISP_SOR_PLL2_0.AUX2(0)
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//PDPLL = SOR_NV_PDISP_SOR_PLL0_0.PWR(1) | SEQ.PDPLL(0) & ~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0)
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//VCOPD = SOR_NV_PDISP_SOR_PLL0_0.VCOPD(1)
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//CAPPD = SOR_NV_PDISP_SOR_PLL2_0.AUX8(1) | SEQ.ASSERT_PLL_RESET(0) &
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//~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0)
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//PDPORT = SOR_NV_PDISP_SOR_PLL2_0.AUX7(1) | SEQ.PDPORT(1) &
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//~ SOR_NV_PDISP_SOR_DP_LINKCTL0_0.ENABLE(0)
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//PDCAL = SOR_NV_PDISP_SOR_DP_PADCTL0_0.PAD_CAL_PD(1)
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// struct clk_rst_ctlr *clkrst =
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// (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE;
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printk(BIOS_SPEW, "%s: entry\n", __func__);
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#if 0
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printk(BIOS_SPEW, "JZ: %s: %d: do nothing, ret\n", __func__, __LINE__);
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return;
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#endif
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sor_clock_stop();
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graphics_clock();
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SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x)
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SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL
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SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x050003D5); //set PWR,VCOPD
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@ -645,7 +596,6 @@ void dp_io_powerup(void)
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SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01C20000); //set AUX1,6,7,8; clr AUX2
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SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220);
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//REG(SOR_NV_PDISP_SOR_PLL3_0,PLLVDD_MODE, V1_8)
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dp_io_set_dpd(0);
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udelay(1); //Deassert E_DPD to enable core logic circuits, and wait for > 5us
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@ -690,8 +640,6 @@ static int dpaux_check(u32 bytes, u32 data, u32 mask)
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printk(BIOS_SPEW, "******AuxRead Error:%04x: status %08x\n", 0x202,
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status);
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else {
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//temp = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0] ;
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//memcpy(&temp, buf, 4);
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temp = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0);
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if ((temp & mask) != (data & mask)) {
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printk(BIOS_SPEW, "AuxCheck ERROR:(r_data) %08x & (mask) %08x != "
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@ -765,7 +713,6 @@ static int dp_training(u32 level, u32 check, u32 speed)
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u32 cnt = 0;
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u32 cfg, cfg_d = 0;
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u32 wcfg;
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// u32 status = 0;
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u8 buf[16];
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while (cnt <= 5) {
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@ -851,11 +798,6 @@ void dp_link_training(u32 lanes, u32 speed)
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udelay(100);
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sor_clock_start();
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#if 0
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reg_val = readl((void *)(0x60006000 + 0x414));
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reg_val |= SOR0_CLK_SEL0;
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writel(reg_val, (void *)(0x60006000 + 0x414));
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#endif
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SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0,
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(((0xF >> (4 - lanes)) << 16) | 1));
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@ -870,10 +812,6 @@ void dp_link_training(u32 lanes, u32 speed)
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printk(BIOS_SPEW, "set link rate and lane number: %dMHz, %d lanes\n",
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(speed * 27), lanes);
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// printk(BIOS_SPEW,"JZ: dbg ret\n");
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// return;
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// %d = (%lanes<<8) | %speed
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dpaux_write(0x100, 2, ((lanes << 8) | speed));
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printk(BIOS_SPEW, "precharge lane 10us\n");
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reg_val = SOR_READ(SOR_NV_PDISP_SOR_DP_PADCTL0_0);
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@ -926,7 +864,6 @@ static u32 div_f(u32 a, u32 b, u32 one)
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u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
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u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
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{
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u32 reg_val;
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u32 pclk_freq = 0;
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///////////////////////////////////////////
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@ -969,27 +906,6 @@ u32 dp_setup_timing(u32 panel_id, u32 width, u32 height)
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return pclk_freq;
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}
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// clock(plld2, %PLL_FREQ) // PLL_FREQ = 570
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writel(0, (void *)(0x60006000 + 0x4bc)); // plld2_misc
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writel(0x13400000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg
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writel(0x8008010c, (void *)(0x60006000 + 0x4b8)); // plld2_base
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writel(0x80105F01, (void *)(0x60006000 + 0x4b8));// plld2_base: 12 * 95 / 2 = 570
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writel(0x40000000, (void *)(0x60006000 + 0x4bc)); // misc: enable lock
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writel(0x80105f01, (void *)(0x60006000 + 0x4b8)); // base: enable
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writel(0xc0105f01, (void *)(0x60006000 + 0x4b8)); // base: check lock
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writel(0x58105f01, (void *)(0x60006000 + 0x4b8)); // base: disable bypass
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writel(0x13800000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg
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udelay(10); // wait for plld2 ready
|
||||
|
||||
// REG(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0, DISP1_CLK_SRC, PLLD2_OUT0)
|
||||
#define DISP1_CLK_SRC (0x7 << 29)
|
||||
#define PLLD2_OUT0 (0x5 << 29)
|
||||
reg_val = readl((void *)(0x60006000 + 0x138));
|
||||
reg_val &= ~DISP1_CLK_SRC;
|
||||
reg_val |= PLLD2_OUT0;
|
||||
writel(reg_val, (void *)(0x60006000 + 0x138));
|
||||
udelay(10);
|
||||
|
||||
PLL_FREQ = PLL_FREQ * 1000000;
|
||||
pclk_freq = PLL_FREQ / PLL_DIV;
|
||||
PLL_FREQ_I = PLL_FREQ / 1000000;
|
||||
|
|
|
|||
|
|
@ -241,7 +241,6 @@ void clock_init(void);
|
|||
void clock_init_arm_generic_timer(void);
|
||||
void sor_clock_stop(void);
|
||||
void sor_clock_start(void);
|
||||
void graphics_clock(void);
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue