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tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb

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These are almost not worth their own CL but I did not want to clutter
up a later CL with them.

BUG=None
TEST=Build, boots, get graphics
BRANCH=None

Change-Id: I16489b767ce01addd522528889878bf5875d197e
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175889
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Ronald G. Minnich 2013-11-05 15:27:23 -08:00 • committed by chrome-internal-fetch
commit 4e513196b0
2 changed files with 6 additions and 1 deletions
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5
src/mainboard/google/nyan/devicetree.cb
View file

@ -28,6 +28,8 @@ chip soc/nvidia/tegra124
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "2560"
register "yres" = "1700"
# this setting is what nvidia does; it makes no sense
# and does not agree with hardware. Why'd they do it?
register "framebuffer_bits_per_pixel" = "24"
register "cache_policy" = "DCACHE_WRITETHROUGH"
@ -67,4 +69,7 @@ chip soc/nvidia/tegra124
register "vfront_porch" = "3"
register "vsync_width" = "10"
register "vback_porch" = "36"
# we *know* the pixel clock for this system.
register "pixel_clock" = "285"
end

2
src/soc/nvidia/tegra124/display.c
View file

@ -87,7 +87,7 @@ static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
};
static int update_display_mode(struct dc_disp_reg *disp,
struct soc_nvidia_tegra124_config *config)
struct soc_nvidia_tegra124_config *config)
{
u32 val;
u32 rate;