broadwell: Add parameters to pei_data structure
- disable_self_refresh: parameter to disable memory self refresh during training. This can be used to work around power issues seen with lpddr3. - disable_saved_data: parameter to disable the use of the cached MRC data. This can be used to work around lpddr3 training replay issues. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None CQ-DEPEND=CL:*169275 TEST=build and boot on samus Change-Id: I051bfbfa0d171ad9b2503cb9a30990b13b4c0cb2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/208153 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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2 changed files with 16 additions and 1 deletions
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@ -31,7 +31,7 @@
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#include <types.h>
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#define PEI_VERSION 20
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#define PEI_VERSION 21
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#define ABI_X86 __attribute__((regparm(0)))
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@ -122,6 +122,8 @@ struct pei_data
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int dq_pins_interleaved;
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/* Limit DDR3 frequency */
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int max_ddr3_freq;
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/* Disable self refresh */
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int disable_self_refresh;
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/* USB port configuration */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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@ -167,6 +169,9 @@ struct pei_data
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const void *saved_data;
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int saved_data_size;
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/* Disable use of saved data (can be set by mainboard) */
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int disable_saved_data;
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/* Data from MRC that should be saved to flash */
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void *data_to_save;
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int data_to_save_size;
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@ -74,6 +74,16 @@ void raminit(struct pei_data *pei_data)
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#endif
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}
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/*
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* Do not use saved pei data. Can be set by mainboard romstage
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* to force a full train of memory on every boot.
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*/
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if (pei_data->disable_saved_data) {
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printk(BIOS_DEBUG, "Disabling PEI saved data by request\n");
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pei_data->saved_data = NULL;
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pei_data->saved_data_size = 0;
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}
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/* Determine if mrc.bin is in the cbfs. */
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entry = (pei_wrapper_entry_t)cbfs_get_file_content(
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CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
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