broadwell: Split SMM related defines/prototypes to new header
This puts all the SMM related information into one location instead of being split across several headers. BUG=chrome-os-partner:28234 TEST=None Change-Id: If4782d37f28b325ff76dd8efa560840d4e1da276 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198738 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
6ac4e56db6
commit
2a25950670
5 changed files with 76 additions and 56 deletions
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@ -134,26 +134,6 @@
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
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/* Sanity check config options. */
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
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#endif
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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#endif
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#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
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# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
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#endif
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#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
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# error "CONFIG_IED_REGION_SIZE is not a power of 2"
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#endif
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#if !defined(__ROMCC__) // FIXME romcc should handle below constructs
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#if defined(__PRE_RAM__)
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@ -196,9 +176,6 @@ void intel_cpu_haswell_finalize_smm(void);
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/* Configure power limits for turbo mode */
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void set_power_limits(u8 power_limit_1_time);
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int cpu_config_tdp_levels(void);
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/* Returns 0 on success, < 0 on failure. */
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int smm_initialize(void);
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void smm_relocate(void);
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struct bus;
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void bsp_init_and_start_aps(struct bus *cpu_bus);
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/* Determine if HyperThreading is disabled. The variable is not valid until
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@ -60,14 +60,6 @@ void pch_log_state(void);
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void acpi_create_intel_hpet(acpi_hpet_t * hpet);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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/* These helpers are for performing SMM relocation. */
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void southbridge_trigger_smi(void);
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void southbridge_clear_smi_status(void);
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/* The initialization of the southbridge is split into 2 compoments. One is
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* for clearing the state in the SMM registers. The other is for enabling
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* SMIs. They are split so that other work between the 2 actions. */
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void southbridge_smm_clear_state(void);
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void southbridge_smm_enable_smi(void);
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#else
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void enable_smbus(void);
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void enable_usb_bar(void);
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73
src/soc/intel/broadwell/broadwell/smm.h
Normal file
73
src/soc/intel/broadwell/broadwell/smm.h
Normal file
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@ -0,0 +1,73 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _BROADWELL_SMM_H_
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#define _BROADWELL_SMM_H_
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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struct ied_header {
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char signature[10];
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u32 size;
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u8 reserved[34];
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} __attribute__ ((packed));
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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/* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE */
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int smm_save_state_in_msrs;
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};
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/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
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* is included after chipset code. This causes the chipset's Kconfig to be
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* cloberred by the arch/x86/Kconfig if they have the same name. */
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static inline int smm_region_size(void)
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{
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/* Make it 8MiB by default. */
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if (CONFIG_SMM_TSEG_SIZE == 0)
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return (8 << 20);
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return CONFIG_SMM_TSEG_SIZE;
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}
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int smm_initialize(void);
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void smm_relocate(void);
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/* These helpers are for performing SMM relocation. */
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void southbridge_trigger_smi(void);
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void southbridge_clear_smi_status(void);
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/* The initialization of the southbridge is split into 2 compoments. One is
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* for clearing the state in the SMM registers. The other is for enabling
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* SMIs. They are split so that other work between the 2 actions. */
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void southbridge_smm_clear_state(void);
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void southbridge_smm_enable_smi(void);
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#endif
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@ -26,8 +26,6 @@
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#define HASWELL_DESKTOP 1
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#define HASWELL_SERVER 2
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/* Intel Enhanced Debug region */
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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#include <southbridge/intel/lynxpoint/pch.h>
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@ -183,12 +181,6 @@
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#ifndef __ASSEMBLER__
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static inline void barrier(void) { asm("" ::: "memory"); }
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struct ied_header {
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char signature[10];
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u32 size;
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u8 reserved[34];
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} __attribute__ ((packed));
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#define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
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#define PCI_DEVICE_ID_HSW_ULT 0x0a04
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@ -49,22 +49,8 @@
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#define SMRR_SUPPORTED (1<<11)
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#define EMRR_SUPPORTED (1<<12)
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struct smm_relocation_params {
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u32 smram_base;
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u32 smram_size;
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u32 ied_base;
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u32 ied_size;
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msr_t smrr_base;
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msr_t smrr_mask;
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msr_t emrr_base;
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msr_t emrr_mask;
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msr_t uncore_emrr_base;
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msr_t uncore_emrr_mask;
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/* The smm_save_state_in_msrs field indicates if SMM save state
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* locations live in MSRs. This indicates to the CPUs how to adjust
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* the SMMBASE and IEDBASE */
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int smm_save_state_in_msrs;
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};
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#include <broadwell/smm.h>
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#include <broadwell/systemagent.h>
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/* This gets filled in and used during relocation. */
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static struct smm_relocation_params smm_reloc_params;
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@ -267,7 +253,7 @@ static void fill_in_relocation_params(device_t dev,
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params->ied_size = tseg_size - params->smram_size;
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/* Adjust available SMM handler memory size. */
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params->smram_size -= RESERVED_SMM_SIZE;
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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