tegra124: Add additional PLLs and redesign the divisor table
This patch intializes the PLLs P, C, D and U in addition to the already existing PLLX. It completely revamps the oscillator-dependent divisor table mechanism, using binary compatible bitfield structs in a transparent union to make it both compact and compile-time range checked while still being readable and easy to use in a generic init_pll() function. It also moves the clock.h file into <soc/...> include space because I'm going to need that for USB code soon. BUG=None TEST=Make sure it still boots as well as before. Change-Id: I5f06f97eb9e0a7359fef02469c63306f500aa423 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174380 Reviewed-by: Ronald Minnich <rminnich@chromium.org>
This commit is contained in:
Julius Werner
chrome-internal-fetch
parent
8d9387432f
commit
f6a5f5c456
6 changed files with 188 additions and 148 deletions
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@ -20,8 +20,8 @@
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/i2c.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra124/clock.h>
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#include <soc/nvidia/tegra124/pinmux.h>
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#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
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@ -21,8 +21,8 @@
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#include <bootblock_common.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/clock.h>
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#include "clock.h"
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#include "pinmux.h"
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#include "power.h"
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@ -326,31 +326,32 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
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#define OSC_FREQ_OSC38P4 5 /* 38.4MHz */
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#define OSC_FREQ_OSC48 9 /* 48.0MHz */
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/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
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#define PLL_BYPASS_SHIFT 31
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#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
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/* CLK_RST_CONTROLLER_PLL*_BASE_0 */
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#define PLL_BASE_BYPASS (1U << 31)
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#define PLL_BASE_ENABLE (1U << 30)
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#define PLL_BASE_REF_DIS (1U << 29)
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#define PLL_BASE_OVRRIDE (1U << 28)
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#define PLL_BASE_LOCK (1U << 27)
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#define PLL_ENABLE_SHIFT 30
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#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
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#define PLL_BASE_DIVP_SHIFT 20
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#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT)
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#define PLL_BASE_OVRRIDE_MASK (1U << 28)
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#define PLL_BASE_LOCK_MASK (1U << 27)
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#define PLL_BASE_DIVN_SHIFT 8
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#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT)
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#define PLL_DIVP_SHIFT 20
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#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
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#define PLL_DIVN_SHIFT 8
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#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
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#define PLL_DIVM_SHIFT 0
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#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
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#define PLL_BASE_DIVM_SHIFT 0
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#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT)
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/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */
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#define PLLCMX_DIVP_MASK (0xfU << PLL_DIVP_SHIFT)
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#define PLLCMX_DIVN_MASK (0xffU << PLL_DIVN_SHIFT)
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#define PLLCMX_DIVM_MASK (0xffU << PLL_DIVM_SHIFT)
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#define PLLCMX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT)
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#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT)
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#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT)
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/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
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/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits
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* on the side that we don't particularly care about. */
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#define PLL_BASE_DIV_MASK (0xffffff)
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/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */
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#define PLL_OUT_RSTN (1 << 0)
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#define PLL_OUT_CLKEN (1 << 1)
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#define PLL_OUT_OVRRIDE (1 << 2)
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@ -365,21 +366,22 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr {
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#define PLL_OUT2_RATIO_SHIFT 24
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#define PLL_OUT2_RATIO_MASK (0xffU << PLL_OUT2_RATIO_SHIFT)
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/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
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#define PLL_DCCON_SHIFT 20
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#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
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/* CLK_RST_CONTROLLER_PLL*_MISC_0 */
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#define PLL_MISC_DCCON (1 << 20)
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#define PLL_LOCK_ENABLE_SHIFT 18
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#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
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#define PLL_MISC_CPCON_SHIFT 8
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#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT)
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#define PLL_CPCON_SHIFT 8
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#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
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#define PLL_MISC_LFCON_SHIFT 4
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#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT)
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#define PLL_LFCON_SHIFT 4
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#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
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/* This bit is different all over the place. Oh joy... */
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#define PLLC_MISC_LOCK_ENABLE (1 << 24)
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#define PLLUD_MISC_LOCK_ENABLE (1 << 22)
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#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18)
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#define PLLE_MISC_LOCK_ENABLE (1 << 9)
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#define PLLU_VCO_FREQ_SHIFT 20
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#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
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#define PLLU_MISC_VCO_FREQ (1 << 20)
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#define PLLP_OUT1_OVR (1 << 2)
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#define PLLP_OUT2_OVR (1 << 18)
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@ -406,19 +408,6 @@ enum {
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IN_408_OUT_9_6_DIVISOR = 83,
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};
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/* CRC_PLLP_MISC_0 0xac */
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#define PLLP_MISC_PLLP_CPCON_8 (8 << 8)
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#define PLLP_MISC_PLLP_LOCK_ENABLE (1 << 18)
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/* CRC_PLLU_BASE_0 0xc0 */
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#define PLLU_BYPASS_ENABLE (1 << 31)
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#define PLLU_ENABLE_ENABLE (1 << 30)
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#define PLLU_REF_DIS_REF_DISABLE (1 << 29)
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#define PLLU_OVERRIDE_ENABLE (1 << 24)
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/* CRC_PLLU_MISC_0 0xcc */
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#define PLLU_LOCK_ENABLE_ENABLE (1 << 22)
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/* PLLX_BASE_0 0xe0 */
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#define PLLX_BASE_PLLX_ENABLE (1 << 30)
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@ -17,8 +17,8 @@
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#include <delay.h>
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#include <arch/io.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include "clk_rst.h"
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#include "clock.h"
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#include "cpug.h"
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#include "flow.h"
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#include "pmc.h"
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@ -27,31 +27,120 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE;
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static struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
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/* only needed in this one place. Avoid namespace pollution. Be green .*/
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struct clk_pll_table {
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u16 n;
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u16 m;
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u8 p;
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struct pll_dividers {
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u32 n : 10;
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u32 m : 8;
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u32 p : 4;
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u32 cpcon: 4;
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u32 : 6;
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};
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/*
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* Timing tables
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*/
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struct clk_pll_table tegra_pll_x_table[16] = {
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/* T124: 1.9 GHz */
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/*
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* Field Bits Width
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* n 15:8 8
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* m 7:0 8
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* p 23:20 4
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*/
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[OSC_FREQ_OSC13]{146,1,0},
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[OSC_FREQ_OSC19P2]{98,1,0},
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[OSC_FREQ_OSC12]{157,1,0},
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[OSC_FREQ_OSC26]{73,1,0},
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[OSC_FREQ_OSC16P8]{113,1,0},
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[OSC_FREQ_OSC38P4]{98,2,0},
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[OSC_FREQ_OSC48]{157,4,0},
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/* Some PLLs have more restrictive divider bit lengths or are missing some
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* fields. Make sure to use the right struct in the osc_table definition to get
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* compile-time checking, but keep the bits aligned with struct pll_dividers so
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* they can be used interchangeably at run time. Add new formats as required. */
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struct pllcx_dividers {
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u32 n : 8;
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u32 : 2;
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u32 m : 8;
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u32 p : 4;
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u32 : 10;
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};
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struct pllpad_dividers {
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u32 n : 10;
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u32 m : 5;
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u32 : 3;
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u32 p : 3;
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u32 : 1;
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u32 cpcon : 4;
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u32 : 6;
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};
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struct pllu_dividers {
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u32 n : 10;
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u32 m : 5;
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u32 : 3;
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u32 p : 1;
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u32 : 3;
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u32 cpcon : 4;
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u32 : 6;
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};
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union __attribute__((transparent_union)) pll_fields {
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u32 raw;
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struct pll_dividers div;
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struct pllcx_dividers cx;
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struct pllpad_dividers pad;
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struct pllu_dividers u;
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};
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/* This table defines the frequency dividers for every PLL to turn the external
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* OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h.
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* All PLLs have three dividers (N, M and P), with the governing formula for
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* the output frequency being OUT = (IN / m) * N / (2^P). */
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struct {
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int khz;
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struct pllcx_dividers pllx; /* target: 1900 MHz */
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struct pllpad_dividers pllp; /* target: 408 MHz */
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struct pllcx_dividers pllc; /* target: 600 MHz */
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struct pllpad_dividers plld; /* target: 925 MHz */
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struct pllu_dividers pllu; /* target; 960 MHz */
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} static const osc_table[16] = {
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[OSC_FREQ_OSC12]{
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.khz = 12000,
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.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
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.pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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},
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[OSC_FREQ_OSC13]{
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.khz = 13000,
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.pllx = {.n = 146, .m = 1, .p = 0}, /* 1898 MHz */
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.pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8},
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.pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */
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.plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12},
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.pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12},
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},
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[OSC_FREQ_OSC16P8]{
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.khz = 16800,
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.pllx = {.n = 113, .m = 1, .p = 0}, /* 1898.4 MHz */
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.pllp = {.n = 170, .m = 7, .p = 0, .cpcon = 4},
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.pllc = {.n = 250, .m = 7, .p = 0},
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.plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8},
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},
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[OSC_FREQ_OSC19P2]{
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.khz = 19200,
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.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
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.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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},
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[OSC_FREQ_OSC26]{
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.khz = 26000,
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.pllx = {.n = 73, .m = 1, .p = 0}, /* 1898 MHz */
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.pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5},
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.pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */
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.plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12},
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.pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8},
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},
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[OSC_FREQ_OSC38P4]{
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.khz = 38400,
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.pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */
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.pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3},
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.pllc = {.n = 125, .m = 4, .p = 0},
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.plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */
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.pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2},
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},
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[OSC_FREQ_OSC48]{
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.khz = 48000,
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.pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */
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.pllp = {.n = 24, .m = 1, .p = 0, .cpcon = 2},
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.pllc = {.n = 50, .m = 1, .p = 0},
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.plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12},
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.pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3},
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},
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};
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void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor)
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@ -73,34 +162,14 @@ void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor)
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* configuration field. This is actually a per-soc thing. Avoid the
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* temptation to make it common.
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*/
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static int clock_get_osc_freq(void)
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static u32 clock_get_osc_bits(void)
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{
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u32 reg;
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reg = readl(&clk_rst->osc_ctrl);
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reg >>= OSC_CTRL_OSC_FREQ_SHIFT;
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return reg;
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return readl(&clk_rst->osc_ctrl) >> OSC_CTRL_OSC_FREQ_SHIFT;
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}
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int clock_get_osc_khz(void)
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{
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/* Implemented better in the next patch, sorry, hard to split this up */
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switch (clock_get_osc_freq()) {
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case OSC_FREQ_OSC13:
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return 13000;
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case OSC_FREQ_OSC19P2:
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return 19200;
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default:
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case OSC_FREQ_OSC12:
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return 12000;
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case OSC_FREQ_OSC26:
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return 26000;
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case OSC_FREQ_OSC16P8:
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return 16800;
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case OSC_FREQ_OSC38P4:
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return 38400;
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case OSC_FREQ_OSC48:
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return 48000;
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}
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return osc_table[clock_get_osc_bits()].khz;
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}
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static void adjust_pllp_out_freqs(void)
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@ -118,54 +187,21 @@ static void adjust_pllp_out_freqs(void)
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writel(reg, &clk_rst->pllp_outb);
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}
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static int pllx_set_rate(u32 divn, u32 divm, u32 divp)
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static void init_pll(u32 *base, u32 *misc, const union pll_fields pll)
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{
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u32 reg;
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u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT |
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pll.div.m << PLL_BASE_DIVM_SHIFT |
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pll.div.p << PLL_BASE_DIVP_SHIFT;
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/* If PLLX is already enabled, just return */
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if (readl(&clk_rst->pllx_base) & PLL_ENABLE_MASK)
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return 0;
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/* Write dividers but BYPASS the PLL while we're messing with it. */
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writel(dividers | PLL_BASE_BYPASS, base);
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/* Disable IDDQ */
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reg = readl(&clk_rst->pllx_misc3);
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reg &= ~PLLX_IDDQ_MASK;
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writel(reg, &clk_rst->pllx_misc3);
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udelay(2);
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/* Set CPCON field (defaults to 0 if it doesn't exist for this PLL) */
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writel(pll.div.cpcon << PLL_MISC_CPCON_SHIFT, misc);
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
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reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
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writel(reg, &clk_rst->pllx_base);
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/* Disable BYPASS */
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reg = readl(&clk_rst->pllx_base);
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &clk_rst->pllx_base);
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/* Set lock_enable to PLLX_MISC */
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reg = readl(&clk_rst->pllx_misc);
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reg |= PLL_LOCK_ENABLE_MASK;
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writel(reg, &clk_rst->pllx_misc);
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/* Enable PLLX last, as per JZ */
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reg = readl(&clk_rst->pllx_base);
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reg |= PLL_ENABLE_MASK;
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writel(reg, &clk_rst->pllx_base);
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return 0;
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}
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static void init_pllx(void)
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{
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int osc = clock_get_osc_freq();
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struct clk_pll_table *sel = &tegra_pll_x_table[osc];
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if (sel->n == 0)
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return;
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pllx_set_rate(sel->n, sel->m, sel->p);
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||||
|
||||
adjust_pllp_out_freqs();
|
||||
/* enable PLL and take it back out of BYPASS (we don't wait for lock
|
||||
* because we assume that to be done by the time we start using it). */
|
||||
writel(dividers | PLL_BASE_ENABLE, base);
|
||||
}
|
||||
|
||||
/* Initialize the UART and put it on CLK_M so we can use it during clock_init().
|
||||
|
|
@ -191,10 +227,6 @@ void clock_cpu0_config_and_reset(void *entry)
|
|||
write32((uintptr_t)entry, &cpug_entry_point);
|
||||
write32((uintptr_t)&cpug_setup, evp_cpu_reset);
|
||||
|
||||
// Wait for PLLX to lock.
|
||||
while (!(readl(&clk_rst->pllx_base) & (0x1 << 27)))
|
||||
;
|
||||
|
||||
// Set up cclk_brst and divider.
|
||||
write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
|
||||
(CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
|
||||
|
|
@ -238,6 +270,7 @@ void clock_cpu0_config_and_reset(void *entry)
|
|||
void clock_init(void)
|
||||
{
|
||||
u32 val;
|
||||
u32 osc = clock_get_osc_bits();
|
||||
|
||||
/*
|
||||
* On poweron, AVP clock source (also called system clock) is set to
|
||||
|
|
@ -270,7 +303,22 @@ void clock_init(void)
|
|||
val |= (OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
|
||||
writel(val, &pmc->osc_edpd_over);
|
||||
|
||||
init_pllx();
|
||||
/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
|
||||
val = readl(&clk_rst->pllx_misc3);
|
||||
val &= ~PLLX_IDDQ_MASK;
|
||||
writel(val, &clk_rst->pllx_misc3);
|
||||
udelay(2);
|
||||
|
||||
/* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */
|
||||
writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2);
|
||||
|
||||
adjust_pllp_out_freqs();
|
||||
|
||||
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx);
|
||||
init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp);
|
||||
init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc);
|
||||
init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld);
|
||||
init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu);
|
||||
|
||||
val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
|
||||
writel(val, &clk_rst->clk_sys_rate);
|
||||
|
|
@ -279,6 +327,7 @@ void clock_init(void)
|
|||
void clock_config(void)
|
||||
{
|
||||
/* Enable clocks for the required peripherals. */
|
||||
/* TODO: can (should?) we use the _SET and _CLR registers here? */
|
||||
setbits_le32(&clk_rst->clk_out_enb_l,
|
||||
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 |
|
||||
CLK_L_SDMMC4);
|
||||
|
|
@ -296,7 +345,7 @@ void clock_config(void)
|
|||
* PLLP base of 408MHz.
|
||||
*/
|
||||
clock_ll_set_source_divisor(&clk_rst->clk_src_mselect, 0,
|
||||
CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
|
||||
CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000));
|
||||
|
||||
/* Give clock time to stabilize */
|
||||
udelay(IO_STABILIZATION_DELAY);
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@
|
|||
#include <cpu/cpu.h>
|
||||
#include <boot/tables.h>
|
||||
#include <cbmem.h>
|
||||
#include <soc/clock.h>
|
||||
#include <soc/nvidia/tegra/dc.h>
|
||||
#include "clk_rst.h"
|
||||
#include "clock.h"
|
||||
#include "chip.h"
|
||||
#include <soc/display.h>
|
||||
|
||||
|
|
@ -255,12 +255,12 @@ void display_startup(device_t dev)
|
|||
setbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1 | CLK_L_HOST1X);
|
||||
|
||||
clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4,
|
||||
CLK_DIVIDER(NVBL_PLLP_KHZ, 144000));
|
||||
CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000));
|
||||
/* u-boot uses PLLC for DISP1.
|
||||
* But the u-boot code does not work and we don't set up PLLC anyway.
|
||||
* PLLP seems quite good enough, so run with that for now. */
|
||||
clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */,
|
||||
CLK_DIVIDER(NVBL_PLLP_KHZ, 600000));
|
||||
CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000));
|
||||
|
||||
udelay(2);
|
||||
|
||||
|
|
|
|||
|
|
@ -156,9 +156,11 @@ enum {
|
|||
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
|
||||
|
||||
/* soc-specific */
|
||||
#define NVBL_PLLP_KHZ (408000)
|
||||
#define NVBL_PLLC_KHZ (600000)
|
||||
#define NVBL_PLLD_KHZ (925000)
|
||||
#define TEGRA_PLLX_KHZ (1900000)
|
||||
#define TEGRA_PLLP_KHZ (408000)
|
||||
#define TEGRA_PLLC_KHZ (600000)
|
||||
#define TEGRA_PLLD_KHZ (925000)
|
||||
#define TEGRA_PLLU_KHZ (960000)
|
||||
|
||||
int clock_get_osc_khz(void);
|
||||
void clock_early_uart(void);
|
||||
Loading…
Add table
Add a link
Reference in a new issue