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tegra124: fix SPI AHB burst length

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The AHB burst length was being set to an invalid value. Apparently
this didn't hurt anything, but we may as well set it correctly.

Also, we don't need to explicitly set AHB_SEQ_WRAP since it defaults
to the value we want.

BUG=none
BRANCH=none
TEST=built and booted on Nyan rev. 0 and 1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Iffb9edeb178ab48876f891d0822a24daae93aa8e
Reviewed-on: https://chromium-review.googlesource.com/177564
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
David Hendricks 2013-11-14 19:41:51 -08:00 • committed by chrome-internal-fetch
commit f292352632
1 changed files with 2 additions and 3 deletions
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5
src/soc/nvidia/tegra124/spi.c
View file

@ -419,9 +419,8 @@ static void setup_dma_params(struct tegra_spi_channel *spi,
/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
* no address wrapping */
clrsetbits_le32(&dma->regs->ahb_seq,
(AHB_BURST_MASK << AHB_BURST_SHIFT) |
(AHB_SEQ_WRAP_MASK << AHB_SEQ_WRAP_SHIFT),
AHB_BURST_MASK << AHB_BURST_SHIFT);
(AHB_BURST_MASK << AHB_BURST_SHIFT),
4 << AHB_BURST_SHIFT);
/* Set ONCE mode to transfer one "block" at a time (64KB) and enable
* flow control. */