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Tegra124: Take the SPI1 controller out of reset and enable its clock.

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This controller is used to communicate with the EC on nyan.

BUG=None
TEST=Built and booted into depthcharge on nyan. With this and other changes,
saw that basic communication with the EC over the SPI bus was possible,
although it didn't work perfectly.
BRANCH=None

Change-Id: I6f487a97b299d4aff4b00e43d8005ded29d8204b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173787
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-10-19 03:17:25 -07:00 • committed by chrome-internal-fetch
commit c026a3fb86
1 changed files with 2 additions and 2 deletions
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4
src/soc/nvidia/tegra124/clock.c
View file

@ -268,7 +268,7 @@ void clock_config(void)
setbits_le32(&clk_rst->clk_out_enb_l,
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1);
setbits_le32(&clk_rst->clk_out_enb_h,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 |
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM);
setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE);
setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT);
@ -302,7 +302,7 @@ void clock_config(void)
clrbits_le32(&clk_rst->rst_dev_l,
CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1);
clrbits_le32(&clk_rst->rst_dev_h,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 |
CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM);
clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE);
clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT);