broadwell: elog: Use chipset_power_state for events
- Change the ELOG code for broadwell to use the chipset_power_state structure found in CBMEM to report events. - Remove the specific handling of non-LP lynxpoint chipset since only the LP variant is supported. - Add a BOOT_STATE_INIT_ENTRY for BS_DEV_INIT to log these events at boot rather than needing to be called separately. BUG=chrome-os-partner:28234 TEST=None Change-Id: I78954ab2ce0a9524a5f591b7feaf0097d0296a51 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199366 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
4383de5846
commit
0ef5961ebe
2 changed files with 66 additions and 119 deletions
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@ -17,171 +17,122 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <arch/acpi.h>
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <stdint.h>
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#include <string.h>
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#include <elog.h>
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#include "pch.h"
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#include <broadwell/lpc.h>
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#include <broadwell/pm.h>
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static void pch_log_standard_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg)
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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{
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u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg);
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u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en;
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/* PME (TODO: determine wake device) */
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if (gpe0_sts & (1 << 11))
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (gpe0_sts & (1 << 13))
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (gpe0_sts & (1 << 7))
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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}
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static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start)
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{
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/* GPE Bank 1 is GPIO 0-31 */
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u32 gpe0_en = inl(get_pmbase() + gpe0_en_reg);
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u32 gpe0_sts = inl(get_pmbase() + gpe0_sts_reg) & gpe0_en;
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int i;
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gpe0_sts &= gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
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}
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}
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static void pch_log_gpe(void)
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static void pch_log_wake_source(struct chipset_power_state *ps)
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{
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int i;
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u16 pmbase = get_pmbase();
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u32 gpe0_sts, gpe0_en;
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int gpe0_high_gpios[] = {
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[0] = 27,
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[24] = 17,
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[25] = 19,
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[26] = 21,
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[27] = 22,
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[28] = 43,
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[29] = 56,
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[30] = 57,
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[31] = 60
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};
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pch_log_standard_gpe(GPE0_EN, GPE0_STS);
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/* GPIO 0-15 */
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gpe0_en = inw(pmbase + GPE0_EN + 2);
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gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en;
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for (i = 0; i <= 15; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
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}
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/*
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* Now check and log upper status bits
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*/
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gpe0_en = inl(pmbase + GPE0_EN_2);
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gpe0_sts = inl(pmbase + GPE0_STS_2) & gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (!gpe0_high_gpios[i])
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continue;
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO,
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gpe0_high_gpios[i]);
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}
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}
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static void pch_lp_log_gpe(void)
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{
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/* Standard GPE are in GPE set 4 */
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pch_log_standard_gpe(LP_GPE0_STS_4, LP_GPE0_EN_4);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(LP_GPE0_STS_1, LP_GPE0_EN_1, 0);
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pch_log_gpio_gpe(LP_GPE0_STS_2, LP_GPE0_EN_2, 32);
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pch_log_gpio_gpe(LP_GPE0_STS_3, LP_GPE0_EN_3, 64);
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}
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void pch_log_state(void)
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{
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u16 pm1_sts, gen_pmcon_3, tco2_sts;
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u8 gen_pmcon_2;
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struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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if (!lpc)
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return;
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pm1_sts = inw(get_pmbase() + PM1_STS);
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tco2_sts = inw(get_pmbase() + TCO2_STS);
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gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
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gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
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/* PWR_FLR Power Failure */
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if (gen_pmcon_2 & (1 << 0))
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (gen_pmcon_3 & (1 << 14))
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* SYS_PWROK Failure */
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if (gen_pmcon_2 & (1 << 1))
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elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
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/* PWROK Failure */
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if (gen_pmcon_2 & (1 << 0))
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elog_add_event(ELOG_TYPE_PWROK_FAIL);
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/* Second TCO Timeout */
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if (tco2_sts & (1 << 1))
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (pm1_sts & (1 << 11))
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* System Reset Status (reset button pushed) */
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if (gen_pmcon_2 & (1 << 4))
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elog_add_event(ELOG_TYPE_RESET_BUTTON);
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/* General Reset Status */
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if (gen_pmcon_3 & (1 << 9))
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake */
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if (pm1_sts & (1 << 15))
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
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acpi_slp_type == 3 ? 3 : 5);
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/*
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* Wake sources
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*/
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/* Power Button */
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if (pm1_sts & (1 << 8))
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (pm1_sts & (1 << 10))
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (pm1_sts & (1 << 14))
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if (ps->pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* GPE */
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if (pch_is_lp())
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pch_lp_log_gpe();
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else
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pch_log_gpe();
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/* PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* Internal PME (TODO: determine wake device) */
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if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
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/* SMBUS Wake */
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if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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/* Log GPIO events in set 1-3 */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64);
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}
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static void pch_log_power_and_resets(struct chipset_power_state *ps)
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{
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/* Thermal Trip Status */
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if (ps->gen_pmcon2 & THERMTRIP_STS)
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elog_add_event(ELOG_TYPE_THERM_TRIP);
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/* PWR_FLR Power Failure */
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if (ps->gen_pmcon2 & PWROK_FLR)
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elog_add_event(ELOG_TYPE_POWER_FAIL);
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/* SUS Well Power Failure */
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if (ps->gen_pmcon3 & SUS_PWR_FLR)
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elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
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/* SYS_PWROK Failure */
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if (ps->gen_pmcon2 & SYSPWR_FLR)
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elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
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/* PWROK Failure */
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if (ps->gen_pmcon2 & PWROK_FLR)
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elog_add_event(ELOG_TYPE_PWROK_FAIL);
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/* Second TCO Timeout */
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if (ps->tco2_sts & TCO2_STS_SECOND_TO)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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/* RTC reset */
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if (ps->gen_pmcon3 & RTC_BATTERY_DEAD)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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/* System Reset Status (reset button pushed) */
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if (ps->gen_pmcon2 & SYSTEM_RESET_STS)
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elog_add_event(ELOG_TYPE_RESET_BUTTON);
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/* General Reset Status */
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if (ps->gen_pmcon3 & GEN_RST_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* ACPI Wake Event */
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if (ps->prev_sleep_state != SLEEP_STATE_S0)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
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}
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static void pch_log_state(void *unused)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL) {
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printk(BIOS_ERR, "Not logging power state information. "
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"Power state not found in cbmem.\n");
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return;
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}
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/* Power and Reset */
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pch_log_power_and_resets(ps);
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/* Wake Sources */
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pch_log_wake_source(ps);
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}
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BOOT_STATE_INIT_ENTRIES(pch_log) = {
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL)
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};
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@ -32,10 +32,6 @@ void southbridge_smm_clear_state(void)
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{
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u32 smi_en;
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#if CONFIG_ELOG
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/* Log events from chipset before clearing */
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pch_log_state();
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#endif
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
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