nyan: Initialize the PMIC.

Add code which initializes the AS3722 PMIC based on the initialization
sequence U-Boot uses. I wasn't able to find documentation which said what each
register in the PMIC does, so the next best solution was to imitate another
implementation which presumably sets things up correctly.

The code is set up significantly differently than the U-Boot code, first
because it uses the i2c driver through it's external interface instead of
poking values into the controller's registers directly. The driver uses the
packet mode of the controller while the U-Boot code does not. Second, it uses
an array of register indices and values, a pattern established with Exynos,
instead of having a sequence of calls to the i2c_write function.

This change is also a practical test of the i2c driver's write capability.

BUG=None
TEST=Built and booted into the bootblock on nyan. Used a multimeter to measure
the voltage on capacitors connected to the CPU's power rail. When booting
U-Boot, the voltage across the capacitors is 1V. When booting coreboot before
this change, that rail stayed off and the rail stayed at 0V. After this change
it went to 1V.
BRANCH=None

Change-Id: Iab1f8d3b735b0737ce93ee3c9c7fdb2a1dcbbf8a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172585
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>

src/mainboard/google/nyan/Makefile.inc

@@ -28,6 +28,7 @@ $(obj)/generated/bct.cfg:
 subdirs-y += bct
 
 bootblock-y += bootblock.c
+bootblock-y += pmic.c
 
 romstage-y += romstage.c
 

src/mainboard/google/nyan/bootblock.c

@@ -24,6 +24,8 @@
 #include <soc/nvidia/tegra124/clock.h>
 #include <soc/nvidia/tegra124/pinmux.h>
 
+#include "pmic.h"
+
 void bootblock_mainboard_init(void)
 {
 	clock_config();
@@ -57,4 +59,6 @@ void bootblock_mainboard_init(void)
 	i2c_init(1);
 	i2c_init(2);
 	i2c_init(4);
+
+	pmic_init(4);
 }

src/mainboard/google/nyan/pmic.c

@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "pmic.h"
+
+struct pmic_write
+{
+	uint8_t reg; // Register to write.
+	uint8_t val; // Value to write.
+};
+
+enum {
+	AS3722_I2C_ADDR = 0x40
+};
+
+static struct pmic_write pmic_writes[] =
+{
+	/* Don't need to set up VDD_CORE - already done - by OTP */
+
+	/* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
+	{ 0x00, 0x28 },
+
+	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+	/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+	{ 0x06, 0x28 },
+
+	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+
+	/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
+	{ 0x12, 0x10 },
+
+	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+
+	/*
+	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	{ 0x16, 0x3f }
+
+	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+};
+
+void pmic_init(unsigned bus)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
+		i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
+			  &pmic_writes[i].val, 1);
+		udelay(10 * 1000);
+	}
+}

src/mainboard/google/nyan/pmic.h

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__
+
+void pmic_init(unsigned bus);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */