tegra124: Add FIFO transmit functions to SPI driver
This patch does a few things: - Add send/receive functions that use the FIFO instead of DMA - Split DMA send/receive functions out - Do not ignore FIFO overrun/underrun errors Aside from making the spi_xfer() function less unwieldy, the main motivation for this is to avoid buffer overruns. It turns out that the DMA engine will always try to work with 4-byte aligned words, so if a input buffer is 5 bytes the DMA engine will clobber the 3 bytes beyond the buffer and cause an Rx underrun. BUG=none BRANCH=none TEST=built and booted on Nyan, no more FIFO overrun errors Change-Id: I696712b44a0a9f41758e89d53d2169de33cfc66f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173639 Commit-Queue: David James <davidjames@chromium.org>
This commit is contained in:
David Hendricks
chrome-internal-fetch
parent
f9dc2a8d80
commit
97e61f36ad
1 changed files with 217 additions and 117 deletions
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@ -279,8 +279,20 @@ static void clear_fifo_status(struct tegra_spi_channel *spi)
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SPI_FIFO_STATUS_RX_FIFO_UNR) << 4);
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}
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static void dump_regs(struct tegra_spi_channel *spi,
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struct apb_dma_channel *dma)
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static void dump_spi_regs(struct tegra_spi_channel *spi)
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{
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printk(BIOS_INFO, "SPI regs:\n"
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"\tdma_blk: 0x%08x\n"
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"\tcommand1: 0x%08x\n"
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"\tdma_ctl: 0x%08x\n"
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"\ttrans_status: 0x%08x\n",
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read32(&spi->regs->dma_blk),
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read32(&spi->regs->command1),
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read32(&spi->regs->dma_ctl),
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read32(&spi->regs->trans_status));
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}
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static void dump_dma_regs(struct apb_dma_channel *dma)
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{
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printk(BIOS_INFO, "DMA regs:\n"
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"\tahb_ptr: 0x%08x\n"
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@ -301,38 +313,76 @@ static void dump_regs(struct tegra_spi_channel *spi,
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read32(&dma->regs->wcount),
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read32(&dma->regs->dma_byte_sta),
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read32(&dma->regs->word_transfer));
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printk(BIOS_INFO, "SPI regs:\n"
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"\tdma_blk: 0x%08x\n"
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"\tcommand1: 0x%08x\n"
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"\tdma_ctl: 0x%08x\n"
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"\ttrans_status: 0x%08x\n",
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read32(&spi->regs->dma_blk),
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read32(&spi->regs->command1),
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read32(&spi->regs->dma_ctl),
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read32(&spi->regs->trans_status));
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}
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int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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void *din, unsigned int bitsin)
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static int tegra_spi_fifo_receive(struct tegra_spi_channel *spi,
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u8 *din, unsigned int in_bytes)
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{
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unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8;
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int ret = 0;
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struct apb_dma_channel *dma;
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struct tegra_spi_channel *spi = to_tegra_spi(slave->bus);
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unsigned int remaining;
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ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0);
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printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes);
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setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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while (in_bytes) {
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remaining = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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in_bytes -= remaining;
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/* tegra bus numbers start at 1 */
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ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels));
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/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
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* PIO transfers */
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write32(remaining - 1, &spi->regs->dma_blk);
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dma = dma_claim();
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if (!dma) {
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printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__);
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return -1;
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != remaining)
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;
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while (remaining) {
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*din = read8(&spi->regs->rx_fifo);
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din++;
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remaining--;
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}
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}
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clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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return in_bytes;
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}
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flush_fifos(spi->regs);
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static int tegra_spi_fifo_send(struct tegra_spi_channel *spi,
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const u8 *dout, unsigned int out_bytes)
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{
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unsigned int remaining;
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printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes);
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setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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while (out_bytes) {
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remaining = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO);
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out_bytes -= remaining;
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/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
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* PIO transfers */
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write32(remaining - 1, &spi->regs->dma_blk);
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while (remaining) {
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write32(*dout, &spi->regs->tx_fifo);
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dout++;
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remaining--;
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}
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
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while (!(read32(&spi->regs->fifo_status) &
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SPI_FIFO_STATUS_TX_FIFO_EMPTY))
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;
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}
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clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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return out_bytes;
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}
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static void tegra2_spi_dma_setup(struct apb_dma_channel *dma)
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{
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/* APB bus width = 8-bits, address wrap for each word */
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clrbits_le32(&dma->regs->apb_seq, 0x7 << 28);
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/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
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@ -341,127 +391,178 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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(0x7 << 24) | (0x7 << 16), 0x4 << 24);
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/* Set ONCE mode to transfer one "blocK" at a time (64KB). */
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setbits_le32(&dma->regs->csr, 1 << 27);
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}
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/*
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* Notes for transmit and receive, experimentally determined (need to
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* verify):
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* - WCOUNT seems to be an "n-1" count, but the documentation does not
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* make this clear. Without the -1 dma_byte_sta will show 1 AHB word
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* (4 bytes) higher than it should and Tx overrun / Rx underrun will
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* likely occur.
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*
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* - dma_byte_sta is always a multiple 4, so we check for
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* dma_byte_sta < length
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*
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* - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually
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* (set bit to clear) between each transaction. Otherwise the next
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* transaction does not start.
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*/
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if (out_bytes && dout) {
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printk(BIOS_SPEW, "%s: Writing %d bytes\n",
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__func__, out_bytes);
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/*
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* Notes for DMA transmit and receive, experimentally determined (need to
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* verify):
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* - WCOUNT seems to be an "n-1" count, but the documentation does not
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* make this clear. Without the -1 dma_byte_sta will show 1 AHB word
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* (4 bytes) higher than it should and Tx overrun / Rx underrun will
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* likely occur.
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*
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* - dma_byte_sta is always a multiple 4, so we check for
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* dma_byte_sta < length
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*
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* - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually
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* (set bit to clear) between each transaction. Otherwise the next
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* transaction does not start.
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*/
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/* set AHB & APB address pointers */
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write32((u32)dout, &dma->regs->ahb_ptr);
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write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr);
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static int tegra_spi_dma_receive(struct tegra_spi_channel *spi,
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const void *din, unsigned int in_bytes)
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{
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struct apb_dma_channel *dma;
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setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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/* FIXME: calculate word count so that it corresponds to bus width */
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write32(out_bytes - 1, &dma->regs->wcount);
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/* specify BLOCK_SIZE in SPI_DMA_BLK */
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write32(out_bytes - 1, &spi->regs->dma_blk);
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/* Set DMA direction for AHB (DRAM) --> APB (SPI) */
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setbits_le32(&dma->regs->csr, (1 << 28));
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/* write to SPI_TRANS_STATUS RDY bit to clear it */
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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dma_start(dma);
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/* set DMA bit in SPI_DMA_CTL to start */
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setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
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/* FIXME: delay loops should be "thread" friendly */
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while ((read32(&dma->regs->dma_byte_sta) < out_bytes) ||
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dma_busy(dma))
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;
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dma_stop(dma);
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != out_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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dma = dma_claim();
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if (!dma) {
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printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__);
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return -1;
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}
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if (in_bytes && din) {
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printk(BIOS_SPEW, "%s: Reading %d bytes\n",
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__func__, in_bytes);
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printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes);
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tegra2_spi_dma_setup(dma);
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/* set AHB & APB address pointers */
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write32((u32)din, &dma->regs->ahb_ptr);
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write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr);
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/* set AHB & APB address pointers */
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write32((u32)din, &dma->regs->ahb_ptr);
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write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr);
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setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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write32(in_bytes - 1, &dma->regs->wcount);
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/* FIXME: calculate word count so that it corresponds to bus width */
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write32(in_bytes - 1, &dma->regs->wcount);
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/* specify BLOCK_SIZE in SPI_DMA_BLK */
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write32(in_bytes - 1, &spi->regs->dma_blk);
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/* specify BLOCK_SIZE in SPI_DMA_BLK */
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write32(in_bytes - 1, &spi->regs->dma_blk);
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/* Set DMA direction for APB (SPI) --> AHB (DRAM) */
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clrbits_le32(&dma->regs->csr, 1 << 28);
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/* Set DMA direction for APB (SPI) --> AHB (DRAM) */
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clrbits_le32(&dma->regs->csr, 1 << 28);
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/* write to SPI_TRANS_STATUS RDY bit to clear it */
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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/* write to SPI_TRANS_STATUS RDY bit to clear it */
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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/* set DMA bit in SPI_DMA_CTL to start */
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setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
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/* set DMA bit in SPI_DMA_CTL to start */
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setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
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/* start APBDMA after SPI DMA so we don't read empty bytes
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* from Rx FIFO */
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dma_start(dma);
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/* start APBDMA after SPI DMA so we don't read empty bytes
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* from Rx FIFO */
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dma_start(dma);
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/* FIXME: delay loops should be "thread" friendly */
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != in_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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/* FIXME: delay loops should be "thread" friendly */
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != in_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
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while ((read32(&dma->regs->dma_byte_sta) < in_bytes) ||
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dma_busy(dma))
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;
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dma_stop(dma);
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while ((read32(&dma->regs->dma_byte_sta) < in_bytes) ||
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dma_busy(dma))
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;
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dma_stop(dma);
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dma_release(dma);
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR)
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dump_dma_regs(dma);
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return in_bytes;
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}
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static int tegra_spi_dma_send(struct tegra_spi_channel *spi,
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const u8 *dout, unsigned int out_bytes)
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{
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struct apb_dma_channel *dma;
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dma = dma_claim();
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if (!dma) {
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printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__);
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return -1;
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}
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printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes);
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tegra2_spi_dma_setup(dma);
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/* set AHB & APB address pointers */
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write32((u32)dout, &dma->regs->ahb_ptr);
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write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr);
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setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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/* FIXME: calculate word count so that it corresponds to bus width */
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write32(out_bytes - 1, &dma->regs->wcount);
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/* specify BLOCK_SIZE in SPI_DMA_BLK */
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write32(out_bytes - 1, &spi->regs->dma_blk);
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/* Set DMA direction for AHB (DRAM) --> APB (SPI) */
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setbits_le32(&dma->regs->csr, (1 << 28));
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/* write to SPI_TRANS_STATUS RDY bit to clear it */
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setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
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dma_start(dma);
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/* set DMA bit in SPI_DMA_CTL to start */
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setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
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/* FIXME: delay loops should be "thread" friendly */
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while ((read32(&dma->regs->dma_byte_sta) < out_bytes) ||
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dma_busy(dma))
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;
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dma_stop(dma);
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while ((read32(&spi->regs->trans_status) &
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SPI_STATUS_BLOCK_COUNT) != out_bytes)
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;
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clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
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dma_release(dma);
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR)
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dump_dma_regs(dma);
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return out_bytes;
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}
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int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout,
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void *din, unsigned int bitsin)
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{
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unsigned int dma_out, dma_in, fifo_out, fifo_in;
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int ret = 0;
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struct tegra_spi_channel *spi = to_tegra_spi(slave->bus);
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u8 *out_buf = (u8 *)dout;
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u8 *in_buf = (u8 *)din;
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ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0);
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/* tegra bus numbers start at 1 */
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ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels));
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flush_fifos(spi->regs);
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/*
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* FIXME: 4-byte unaligned transfers will cause FIFO overrun/underruns.
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* The DMA controller will attempt to send/receive more bytes than it
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* should, but the SPI controller is smart enough not to attempt to
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* transmit more bytes than BLOCK_SIZE in the SPI_DMA_BLK register.
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* DMA operates on 4 bytes at a time, so to avoid accessing memory
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* outside the specified buffers we'll only use DMA for 4-byte aligned
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* transactions accesses and transfer remaining bytes using FIFO access.
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*/
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if (din && (in_bytes % 4)) {
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if (read32(&spi->regs->fifo_status) &
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SPI_FIFO_STATUS_RX_FIFO_UNR) {
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printk(BIOS_DEBUG, "SPI: Ignoring Rx FIFO underrun.\n");
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setbits_le32(&spi->regs->fifo_status,
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SPI_FIFO_STATUS_RX_FIFO_UNR);
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}
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fifo_out = (bitsout / 8) % TEGRA_DMA_ALIGN_BYTES;
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dma_out = (bitsout / 8) - fifo_out;
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fifo_in = (bitsin / 8) % TEGRA_DMA_ALIGN_BYTES;
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dma_in = (bitsin / 8) - fifo_in;
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if (dma_out) {
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tegra_spi_dma_send(spi, out_buf, dma_out);
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out_buf += dma_out;
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}
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if (dout && (out_bytes % 4)) {
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if (read32(&spi->regs->fifo_status) &
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SPI_FIFO_STATUS_TX_FIFO_OVF) {
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printk(BIOS_DEBUG, "SPI: Ignoring Tx FIFO overrun.\n");
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setbits_le32(&spi->regs->fifo_status,
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SPI_FIFO_STATUS_TX_FIFO_OVF);
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}
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if (fifo_out)
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tegra_spi_fifo_send(spi, out_buf, fifo_out);
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if (dma_in) {
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tegra_spi_dma_receive(spi, in_buf, dma_in);
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in_buf += dma_in;
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}
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if (fifo_in)
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tegra_spi_fifo_receive(spi, in_buf, fifo_in);
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if (read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR) {
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ret = -1;
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dump_regs(spi, dma);
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dump_spi_regs(spi);
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print_fifo_status(spi);
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clear_fifo_status(spi);
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}
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@ -499,7 +600,6 @@ static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest,
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int ret = count;
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/* TODO: Dual mode (BOTH_EN_BIT) and packed mode */
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spi_read_cmd[0] = JEDEC_READ;
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spi_read_cmd[1] = (offset >> 16) & 0xff;
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||||
spi_read_cmd[2] = (offset >> 8) & 0xff;
|
||||
|
|
|
|||
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Add table
Add a link
Reference in a new issue