broadwell: smbus: Extract common code and split header
Move the smbus romstage/ramstage related code into smbus_common.c and split out the smbus related defines/prototypes from pch.h to broadwell/smbus.h. BUG=chrome-os-partner:28234 TEST=None Change-Id: Ide534ee8d13868fb3ab0a277c958b862c5dfeeb7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198735 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
f93b8bda71
commit
8052030a9d
4 changed files with 186 additions and 156 deletions
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@ -122,7 +122,6 @@ void southbridge_smm_enable_smi(void);
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#else
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void enable_smbus(void);
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void enable_usb_bar(void);
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int smbus_read_byte(unsigned device, unsigned address);
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int early_spi_read(u32 offset, u32 size, u8 *buffer);
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int early_pch_init(const void *gpio_map,
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const struct rcba_config_instruction *rcba_config);
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@ -155,33 +154,6 @@ void pch_enable_lpc(void);
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#define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
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#define PCH_PCIE_DEV_SLOT 28
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/* PCI Configuration Space (D31:F3): SMBus */
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#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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#define SMB_RCV_SLVA 0x09
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* SMBus I/O bits. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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/* Southbridge IO BARs */
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#define GPIOBASE 0x48
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@ -19,83 +19,34 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/smbus_def.h>
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#include "pch.h"
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#ifndef _BROADWELL_SMBUS_H_
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#define _BROADWELL_SMBUS_H_
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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/* PCI Configuration Space (D31:F3): SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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#define HST_EN (1 << 0)
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#define SMB_RCV_SLVA 0x09
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & 1);
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return loops ? 0 : -1;
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}
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/* SMBus I/O bits. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
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return loops ? 0 : -1;
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}
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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#define SMBUS_SLAVE_ADDR 0x24
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static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1)) {
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return SMBUS_ERROR;
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}
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return byte;
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}
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int do_smbus_read_byte(unsigned smbus_base, unsigned device,
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unsigned address);
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int do_smbus_write_byte(unsigned smbus_base, unsigned device,
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unsigned address, unsigned data);
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#endif
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@ -58,54 +58,6 @@ static int lsmbus_read_byte(device_t dev, u8 address)
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return do_smbus_read_byte(res->base, device, address);
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}
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static int do_smbus_write_byte(unsigned smbus_base, unsigned device,
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unsigned address, unsigned data)
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{
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unsigned char global_status_register;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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printk(BIOS_ERR, "SMBUS transaction timeout\n");
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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if (global_status_register != (1 << 1)) {
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printk(BIOS_ERR, "SMBUS transaction error\n");
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return SMBUS_ERROR;
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}
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return 0;
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}
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static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
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{
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u16 device;
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155
src/soc/intel/broadwell/smbus_common.c
Normal file
155
src/soc/intel/broadwell/smbus_common.c
Normal file
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@ -0,0 +1,155 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/smbus_def.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <broadwell/ramstage.h>
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#include <broadwell/smbus.h>
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & 1);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
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return loops ? 0 : -1;
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}
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int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1)) {
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return SMBUS_ERROR;
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}
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return byte;
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}
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int do_smbus_write_byte(unsigned smbus_base, unsigned device,
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unsigned address, unsigned data)
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{
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unsigned char global_status_register;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking too */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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printk(BIOS_ERR, "SMBUS transaction timeout\n");
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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if (global_status_register != (1 << 1)) {
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printk(BIOS_ERR, "SMBUS transaction error\n");
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return SMBUS_ERROR;
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}
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return 0;
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}
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