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tegra124: Change the display hack to use window A

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The hack seems to set up coreboot display to use window B.  We eventually
want to use the same window as the kernel is going to use (I think), so
that's what this patch does.

We think window B is hiding the contents of window A, which is why we
weren't seeing ChromeOS UI come up.  This fix makes that not happen anymore
by making coreboot use window A.

BUG=chrome-os-partner:24844
TEST=Can boot ChromeOS to UI from coreboot.

Change-Id: I24b95200ba2e8eaeadecd45392ccee5e270aa7da
Reviewed-on: https://chromium-review.googlesource.com/182001
Tested-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
This commit is contained in:
Andrew Chew 2014-01-08 16:49:08 -08:00 • committed by chrome-internal-fetch
commit ef245e42eb
2 changed files with 15 additions and 13 deletions
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24
src/soc/nvidia/tegra124/displayhack.c
View file

@ -669,14 +669,15 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT));
}
DCA_WRITE(DC_B_WIN_BD_SIZE_0, ((height << 16) | width));
DCA_WRITE(DC_B_WIN_BD_PRESCALED_SIZE_0,
DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000010);
DCA_WRITE(DC_WIN_A_SIZE_0, ((height << 16) | width));
DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0,
((height << 16) | (width * SRC_BPP / 8)));
DCA_WRITE(DC_B_WIN_BD_LINE_STRIDE_0,
DCA_WRITE(DC_WIN_A_LINE_STRIDE_0,
((width * SRC_BPP / 8 + 31) / 32 * 32));
DCA_WRITE(DC_B_WIN_BD_COLOR_DEPTH_0, COLORDEPTH);
DCA_WRITE(DC_B_WINBUF_BD_START_ADDR_0, winb_addr);
DCA_WRITE(DC_B_WIN_BD_DDA_INCREMENT_0, 0x10001000);
DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, COLORDEPTH);
DCA_WRITE(DC_WINBUF_A_START_ADDR_LO_0, winb_addr);
DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x10001000);
SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000001);
DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000009); //CRC_ALWAYS+CRC_ENABLE
@ -687,7 +688,6 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000020);
SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000e48);
dpaux_write(0x101, 1, (enhanced_framing << 7) | lane_count);
if (panel_edp)
dpaux_write(0x10A, 1, 1);
@ -731,10 +731,8 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4);
DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff);
/* enable win_b */
DCA_READ_M_WRITE(DC_B_WIN_BD_WIN_OPTIONS_0,
DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD,
(DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE <<
DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT));
DCA_READ_M_WRITE(DC_WIN_A_WIN_OPTIONS_0,
DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD,
(DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE <<
DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT));
}

4
src/soc/nvidia/tegra124/include/soc/display.h
View file

@ -44,6 +44,9 @@
/* ardisplay_a.h */
#define DC_WIN_A_WIN_OPTIONS_0 0x700
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT)
#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1)
#define DC_WIN_A_BYTE_SWAP_0 0x701
#define DC_WIN_A_BUFFER_CONTROL_0 0x702
#define DC_WIN_A_COLOR_DEPTH_0 0x703
@ -59,6 +62,7 @@
#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717
#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718
#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719
#define DC_WINBUF_A_START_ADDR_LO_0 0x800
#define DC_WINBUF_A_START_ADDR_HI_0 0x80d
#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806
#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808