broadwell: Clean up XHCI and EHCI ramstage drivers
The EHCI controller is disabled in refcode binary in the typical case, it is only left enabled when using USBDEBUG. So the code to disable the controller can be removed. The XHCI controller clock gating setup is done in the ramstage refcode binary so that code can be removed now. The SMM code for preparing the controller prior to S3/S5 is reworked but still made available to be called by the SMI handler. BUG=chrome-os-partner:28234 TEST=None Change-Id: I19d1df99d2ee5dbc9c93ca01b2d246432928d77f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/199181 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie
chrome-internal-fetch
parent
d8fc9daf12
commit
d355247333
2 changed files with 26 additions and 370 deletions
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@ -23,150 +23,9 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "pch.h"
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#include <usbdebug.h>
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#include <arch/io.h>
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#ifdef __SMM__
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void usb_ehci_disable(device_t dev)
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{
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u16 reg16;
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u32 reg32;
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/* Set 0xDC[0]=1 */
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pci_or_config32(dev, 0xdc, (1 << 0));
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/* Set D3Hot state and disable PME */
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reg16 = pci_read_config16(dev, EHCI_PWR_CTL_STS);
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reg16 &= ~(PWR_CTL_ENABLE_PME | PWR_CTL_SET_MASK);
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reg16 |= PWR_CTL_SET_D3;
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pci_write_config16(dev, EHCI_PWR_CTL_STS, reg16);
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/* Clear memory and bus master */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Disable device */
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switch (dev) {
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case PCH_EHCI1_DEV:
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RCBA32_OR(FD, PCH_DISABLE_EHCI1);
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break;
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case PCH_EHCI2_DEV:
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RCBA32_OR(FD, PCH_DISABLE_EHCI2);
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break;
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}
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}
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/* Handler for EHCI controller on entry to S3/S4/S5 */
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void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
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{
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u32 reg32;
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u32 bar0_base;
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u16 pwr_state;
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u16 pci_cmd;
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/* Check if the controller is disabled or not present */
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bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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if (bar0_base == 0 || bar0_base == 0xffffffff)
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return;
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pci_cmd = pci_read_config32(dev, PCI_COMMAND);
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switch (slp_typ) {
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case SLP_TYP_S4:
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case SLP_TYP_S5:
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/* Check if controller is in D3 power state */
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pwr_state = pci_read_config16(dev, EHCI_PWR_CTL_STS);
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if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
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/* Put in D0 */
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u32 new_state = pwr_state & ~PWR_CTL_SET_MASK;
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new_state |= PWR_CTL_SET_D0;
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pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state);
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/* Make sure memory bar is set */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base);
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/* Make sure memory space is enabled */
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pci_write_config16(dev, PCI_COMMAND, pci_cmd |
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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}
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/*
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* If Run/Stop (bit0) is clear in USB2.0_CMD:
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* - Clear Async Schedule Enable (bit5) and
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* - Clear Periodic Schedule Enable (bit4) and
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* - Set Run/Stop (bit0)
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*/
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reg32 = read32(bar0_base + EHCI_USB_CMD);
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if (reg32 & EHCI_USB_CMD_RUN) {
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reg32 &= ~(EHCI_USB_CMD_PSE | EHCI_USB_CMD_ASE);
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reg32 |= EHCI_USB_CMD_RUN;
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write32(bar0_base + EHCI_USB_CMD, reg32);
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}
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/* Check for Port Enabled in PORTSC(0) (RMH) */
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reg32 = read32(bar0_base + EHCI_PORTSC(0));
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if (reg32 & EHCI_PORTSC_ENABLED) {
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/* Set suspend bit in PORTSC if not already set */
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if (!(reg32 & EHCI_PORTSC_SUSPEND)) {
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reg32 |= EHCI_PORTSC_SUSPEND;
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write32(bar0_base + EHCI_PORTSC(0), reg32);
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}
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/* Delay 25ms !! */
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udelay(25 * 1000);
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/* Clear Run/Stop bit */
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reg32 = read32(bar0_base + EHCI_USB_CMD);
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reg32 &= EHCI_USB_CMD_RUN;
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write32(bar0_base + EHCI_USB_CMD, reg32);
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}
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/* Restore state to D3 if that is what it was at the start */
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if ((pwr_state & PWR_CTL_SET_MASK) == PWR_CTL_SET_D3) {
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/* Restore pci command reg */
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pci_write_config16(dev, PCI_COMMAND, pci_cmd);
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/* Enable D3 */
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pci_write_config16(dev, EHCI_PWR_CTL_STS, pwr_state);
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}
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}
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}
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#else /* !__SMM__ */
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static void usb_ehci_clock_gating(struct device *dev)
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{
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u32 reg32;
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/* IOBP 0xE5004001[7:6] = 11b */
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pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
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/* Dx:F0:DCh[5,2,1] = 111b
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* Dx:F0:DCh[0] = 1b when EHCI controller is disabled */
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reg32 = pci_read_config32(dev, 0xdc);
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reg32 |= (1 << 5) | (1 << 2) | (1 << 1);
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pci_write_config32(dev, 0xdc, reg32);
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/* Dx:F0:78h[1:0] = 11b */
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reg32 = pci_read_config32(dev, 0x78);
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reg32 |= (1 << 1) | (1 << 0);
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pci_write_config32(dev, 0x78, reg32);
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}
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static void usb_ehci_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
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usb_ehci_clock_gating(dev);
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/* Disable Wake on Disconnect in RMH */
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RCBA32_OR(0x35b0, 0x00000022);
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printk(BIOS_DEBUG, "done.\n");
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}
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#include <broadwell/ehci.h>
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static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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@ -233,5 +92,3 @@ static const struct pci_driver pch_usb_ehci __pci_driver = {
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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#endif /* !__SMM__ */
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@ -23,11 +23,10 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include "pch.h"
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typedef struct southbridge_intel_lynxpoint_config config_t;
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#include <broadwell/ramstage.h>
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#include <broadwell/xhci.h>
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#ifdef __SMM__
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static u32 usb_xhci_mem_base(device_t dev)
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{
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u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -41,23 +40,8 @@ static u32 usb_xhci_mem_base(device_t dev)
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static int usb_xhci_port_count_usb3(device_t dev)
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{
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if (pch_is_lp()) {
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/* LynxPoint-LP has 4 SS ports */
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return 4;
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} else {
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/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
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u32 mem_base = usb_xhci_mem_base(dev);
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u32 fus = read32(mem_base + XHCI_USB3FUS);
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fus >>= XHCI_USB3FUS_SS_SHIFT;
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fus &= XHCI_USB3FUS_SS_MASK;
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switch (fus) {
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case 3: return 0;
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case 2: return 2;
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case 1: return 4;
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case 0: default: return 6;
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}
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}
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return 0;
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/* PCH-LP has 4 SS ports */
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return 4;
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}
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static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
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@ -157,8 +141,6 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
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usb_xhci_reset_status_usb3(mem_base, port);
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}
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#ifdef __SMM__
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/* Handler for XHCI controller on entry to S3/S4/S5 */
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void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
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{
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@ -169,219 +151,36 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
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if (!mem_base || slp_typ < 3)
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return;
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if (pch_is_lp()) {
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/* Set D0 state */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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/* Clear PCI 0xB0[14:13] */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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pci_write_config32(dev, 0xb0, reg32);
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/* Clear MMIO 0x816c[14,2] */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~((1 << 14) | (1 << 2));
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write32(mem_base + 0x816c, reg32);
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/* Reset disconnected USB3 ports */
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usb_xhci_reset_usb3(dev, 0);
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/* Set MMIO 0x80e0[15] */
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reg32 = read32(mem_base + 0x80e0);
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reg32 |= (1 << 15);
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write32(mem_base + 0x80e0, reg32);
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}
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/* Set D3Hot state and enable PME */
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_SET_D3);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_STATUS_PME);
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pci_or_config16(dev, XHCI_PWR_CTL_STS, PWR_CTL_ENABLE_PME);
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}
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/* Route all ports to XHCI controller */
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void usb_xhci_route_all(void)
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{
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u32 port_mask, route;
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u16 reg16;
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/* Skip if EHCI is already disabled */
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if (RCBA32(FD) & PCH_DISABLE_EHCI1)
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return;
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/* Set D0 state */
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reg16 = pci_read_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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pci_write_config16(PCH_XHCI_DEV, XHCI_PWR_CTL_STS, reg16);
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/* Set USB3 superspeed enable */
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port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PRM);
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route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB3PR);
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route &= ~XHCI_USB3PR_SSEN;
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route |= XHCI_USB3PR_SSEN & port_mask;
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pci_write_config32(PCH_XHCI_DEV, XHCI_USB3PR, route);
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/* Route USB2 ports to XHCI controller */
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port_mask = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PRM);
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route = pci_read_config32(PCH_XHCI_DEV, XHCI_USB2PR);
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route &= ~XHCI_USB2PR_HCSEL;
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route |= XHCI_USB2PR_HCSEL & port_mask;
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pci_write_config32(PCH_XHCI_DEV, XHCI_USB2PR, route);
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/* Disable EHCI controller */
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usb_ehci_disable(PCH_EHCI1_DEV);
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/* LynxPoint-H has a second EHCI controller */
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if (!pch_is_lp())
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usb_ehci_disable(PCH_EHCI2_DEV);
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/* Reset and clear port change status */
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usb_xhci_reset_usb3(PCH_XHCI_DEV, 1);
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}
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#else /* !__SMM__ */
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static void usb_xhci_clock_gating(device_t dev)
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{
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u32 reg32;
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u16 reg16;
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/* IOBP 0xE5004001[7:6] = 11b */
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pch_iobp_update(0xe5004001, ~0, (1 << 7)|(1 << 6));
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reg32 = pci_read_config32(dev, 0x40);
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reg32 &= ~(1 << 23); /* unsupported request */
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if (pch_is_lp()) {
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/* D20:F0:40h[18,17,8] = 111b */
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reg32 |= (1 << 18) | (1 << 17) | (1 << 8);
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/* D20:F0:40h[21,20,19] = 110b to enable XHCI Idle L1 */
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reg32 &= ~(1 << 19);
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reg32 |= (1 << 21) | (1 << 20);
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} else {
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/* D20:F0:40h[21,20,18,17,8] = 11111b */
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reg32 |= (1 << 21)|(1 << 20)|(1 << 18)|(1 << 17)|(1 << 8);
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}
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/* Avoid writing upper byte as it is write-once */
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pci_write_config16(dev, 0x40, (u16)(reg32 & 0xffff));
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pci_write_config8(dev, 0x40 + 2, (u8)((reg32 >> 16) & 0xff));
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/* D20:F0:44h[9,7,3] = 111b */
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reg16 = pci_read_config16(dev, 0x44);
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reg16 |= (1 << 9) | (1 << 7) | (1 << 3);
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pci_write_config16(dev, 0x44, reg16);
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reg32 = pci_read_config32(dev, 0xa0);
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if (pch_is_lp()) {
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/* D20:F0:A0h[18] = 1 */
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reg32 |= (1 << 18);
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} else {
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/* D20:F0:A0h[6] = 1 */
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reg32 |= (1 << 6);
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}
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pci_write_config32(dev, 0xa0, reg32);
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/* D20:F0:A4h[13] = 0 */
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reg32 = pci_read_config32(dev, 0xa4);
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reg32 &= ~(1 << 13);
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pci_write_config32(dev, 0xa4, reg32);
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}
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static void usb_xhci_init(device_t dev)
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{
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u32 reg32;
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u16 reg16;
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u32 mem_base = usb_xhci_mem_base(dev);
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config_t *config = dev->chip_info;
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/* D20:F0:74h[1:0] = 00b (set D0 state) */
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reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
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reg16 &= ~PWR_CTL_SET_MASK;
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reg16 |= PWR_CTL_SET_D0;
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reg16 &= ~XHCI_PWR_CTL_SET_MASK;
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reg16 |= XHCI_PWR_CTL_SET_D0;
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pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
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/* Enable clock gating first */
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usb_xhci_clock_gating(dev);
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/* Clear PCI 0xB0[14:13] */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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pci_write_config32(dev, 0xb0, reg32);
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reg32 = read32(mem_base + 0x8144);
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if (pch_is_lp()) {
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/* XHCIBAR + 8144h[8,7,6] = 111b */
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reg32 |= (1 << 8) | (1 << 7) | (1 << 6);
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} else {
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/* XHCIBAR + 8144h[8,7,6] = 100b */
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reg32 &= ~((1 << 7) | (1 << 6));
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reg32 |= (1 << 8);
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}
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write32(mem_base + 0x8144, reg32);
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/* Clear MMIO 0x816c[14,2] */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~((1 << 14) | (1 << 2));
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write32(mem_base + 0x816c, reg32);
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if (pch_is_lp()) {
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/* XHCIBAR + 816Ch[19:0] = 000e0038h */
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reg32 = read32(mem_base + 0x816c);
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reg32 &= ~0x000fffff;
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reg32 |= 0x000e0038;
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write32(mem_base + 0x816c, reg32);
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/* Reset disconnected USB3 ports */
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usb_xhci_reset_usb3(dev, 0);
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/* D20:F0:B0h[17,14,13] = 100b */
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reg32 = pci_read_config32(dev, 0xb0);
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reg32 &= ~((1 << 14) | (1 << 13));
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reg32 |= (1 << 17);
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pci_write_config32(dev, 0xb0, reg32);
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}
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/* Set MMIO 0x80e0[15] */
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reg32 = read32(mem_base + 0x80e0);
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reg32 |= (1 << 15);
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write32(mem_base + 0x80e0, reg32);
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reg32 = pci_read_config32(dev, 0x50);
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if (pch_is_lp()) {
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/* D20:F0:50h[28:0] = 0FCE2E5Fh */
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reg32 &= ~0x1fffffff;
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reg32 |= 0x0fce2e5f;
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} else {
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/* D20:F0:50h[26:0] = 07886E9Fh */
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reg32 &= ~0x07ffffff;
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reg32 |= 0x07886e9f;
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}
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||||
pci_write_config32(dev, 0x50, reg32);
|
||||
|
||||
/* D20:F0:44h[31] = 1 (Access Control Bit) */
|
||||
reg32 = pci_read_config32(dev, 0x44);
|
||||
reg32 |= (1 << 31);
|
||||
pci_write_config32(dev, 0x44, reg32);
|
||||
|
||||
/* D20:F0:40h[31,23] = 10b (OC Configuration Done) */
|
||||
reg32 = pci_read_config32(dev, 0x40);
|
||||
reg32 &= ~(1 << 23); /* unsupported request */
|
||||
reg32 |= (1 << 31);
|
||||
pci_write_config32(dev, 0x40, reg32);
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME
|
||||
if (acpi_slp_type == 3) {
|
||||
/* Reset ports that are disabled or
|
||||
* polling before returning to the OS. */
|
||||
usb_xhci_reset_usb3(dev, 0);
|
||||
} else
|
||||
#endif
|
||||
/* Route all ports to XHCI */
|
||||
if (config->xhci_default)
|
||||
outb(0xca, 0xb2);
|
||||
/* Set D3Hot state and enable PME */
|
||||
pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3);
|
||||
pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_STATUS_PME);
|
||||
pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_ENABLE_PME);
|
||||
}
|
||||
|
||||
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
|
||||
unsigned device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
pci_read_config32(dev, PCI_VENDOR_ID));
|
||||
} else {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
}
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = &usb_xhci_set_subsystem,
|
||||
};
|
||||
#else /* !__SMM__ */
|
||||
|
||||
static struct device_operations usb_xhci_ops = {
|
||||
.read_resources = &pci_dev_read_resources,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue