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tegra124: Rearrange iRAM layout to allow more space for romstage

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With all the stuff we have been cramming into our romstage lately, 36KB
isn't really going to cut it anymore. While we should think about other
measures to keep our image size down for the sake of boot time, this
patch provides some quick relief to allow us to move on for a while. It
rearranges the iRAM layout to make more use of the pre-0x4000e000 region
after the BootROM is gone and reduces the size of the CBFS cache a bit
in favor of bootblock and romstage.

BUG=None
TEST=nyan_big boots on my Norrin, even if I have 16 SDRAM param tables.

Change-Id: I3072077978b1f34d222f1844491c5c038d433b85
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184240
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Julius Werner 2014-01-28 15:23:35 -08:00 • committed by chrome-internal-fetch
commit 6bdaabbc06
1 changed files with 16 additions and 17 deletions
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33
src/soc/nvidia/tegra124/Kconfig
View file

@ -29,17 +29,15 @@ config BOOTBLOCK_CPU_INIT
# 0x18080 Free for CBFS data.
#
# iRAM (256k) layout.
# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM.
# +0000 (BootROM) Boot Information Table.
# +0100 (BootROM) BCT.
# ---------------------------------------------------------------------
# +0000 (Coreboot) TTB 16KB.
# +4000 (Coreboot) Stack.
# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry
# point address specified in BCT).
# +0000 (Coreboot) Bootblock (max 36k).
# +9000 (Coreboot) ROM stage (max 36k).
# 0x4002_0000 (Coreboot) Cache of CBFS.
# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
# so the bootblock loading address must be placed after that. After the
# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
#
# 0x4000_0000 TTB (16KB).
# 0x4000_4000 CBFS mapping cache (96KB).
# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# 0x4002_0000 Bootblock (max 48KB).
# 0x4002_C000 ROM stage (max 80KB).
# 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET
@ -60,11 +58,11 @@ config SYS_SDRAM_BASE
config BOOTBLOCK_BASE
hex
default 0x4000e000
default 0x40020000
config ROMSTAGE_BASE
hex
default 0x40017000
default 0x4002c000
config RAMSTAGE_BASE
hex
@ -72,12 +70,13 @@ config RAMSTAGE_BASE
config STACK_TOP
hex
default 0x4000c000
default 0x40020000
config STACK_BOTTOM
hex
default 0x40004000
default 0x4001c000
# This is the ramstage thread stack, *not* the same as above! Currently unused.
config STACK_SIZE
hex
default 0x800
@ -89,11 +88,11 @@ config TTB_BUFFER
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x40020000
default 0x40004000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00020000
default 0x00018000
choice CONSOLE_SERIAL_TEGRA124_UART_CHOICES
prompt "Serial Console UART"